Abstract: A circuit module includes at least one high temperature semiconductor chip having chip pads; a substrate having substrate metallization, the chip pads and the substrate metallization being substantially planar; and a deposited flexible pattern of electrical conductors capable of withstanding high temperatures and coupling selected chip pads and portions of the substrate metallization. The deposited flexible pattern of electrical conductors includes a plurality of integral interconnect segments, at least one of the integral interconnect segments including first and second leg portions and a shelf portion with the shelf portion being spaced apart from the at least one semiconductor chip and substrate and being coupled by the first leg portion to a selected chip pad and by the second leg portion to one of another selected chip pad or a selected portion of the substrate metallization.

Abstract: A flexible film interface includes a flexible film; flexible material attached to a portion of the flexible film; surface metallization on the flexible material, the flexible film having at least one via extending therethrough to the surface metallization; and a floating pad structure including floating pad metallization patterned over the flexible material and the surface metallization, a first portion of the floating pad metallization forming a central pad and a second portion of the floating pad metallization forming at least one extension from the central pad and extending into the at least one via.

Abstract: An interface includes a surface having an electrically conductive pad; a compliant coating over the surface having a via extending to the pad; metallization patterned over the compliant coating and extending into the via; a low modulus dielectric interface layer overlying the compliant coating and having an interface via extending to the metallization; and a floating pad structure including floating pad metallization patterned over the dielectric interface layer with a first portion forming a central pad and a second portion forming an extension from the central pad extending into the interface via. Another interface includes a substrate including a low modulus dielectric interface material having a hole extending at least partially therethrough and a floating contact structure including electrically conductive material coating the hole with at least some of the floating pad metallization forming an extension from the hole.

Abstract: For fully testing and burning-in an integrated circuit chip before it is incorporated into a high density interconnect or other standard hybrid bare chip circuit, a temporary test substrate having pins extending therethrough holds the chip within a cavity. Chip pads are electrically connected with the pins to create a package that can be tested using commercially available testing and burn-in devices. After testing, the chip is retrieved from the test structure undamaged. In using HDI techniques to interconnect the chip with the pins, metal-filled vias in a polymer layer overlying the temporary test substrate electrically connect the chip to the pins through a metal interconnect pattern on the polymer layer. In another embodiment, the chip is interconnected with the pins through wire bonds. Metal-filled vias pass through an insulative coating on the chip and make electrical contact with the chip pad.

Abstract: Top die pads are electrically relocated by forming holes through a semiconductor wafer between device active regions. An electrically insulating layer is formed over all exposed surfaces of the wafer, including within the holes, and openings are made in the insulating layer for access to the top interconnection pads. The wafer and holes are metallized and patterned to form bottom interconnection pads electrically connected to corresponding top interconnection pads by metallization extending within the holes. A dicing saw having a kerf width less than the diameter of the holes is employed to separate the individual devices. For accurate position alignment of repatterned die, an alignment structure, such as projecting pins or an egg crate structure, engages the die, and alignment pads can be patterned on the die.

Abstract: A method is provided for the manufacture of precision electronic components such as resistors, inductors, and capacitors on a polymer or ceramic surface. The electronic components can be deposited and trimmed to precise or matched values without having precise depositions of all of the pre-patterned materials. Thin film electronic components are deposited on a surface, parameter values are measured or estimated, a correction offset file is generated, and the components are trimmed using adaptive lithography to a very close tolerance. A computer program can be used to enable the adjustment of electronic components by techniques such as changing the physical length of an inductor coil or resistor lead, or by changing a capacitor plate area.

Abstract: A high density interconnected multi-chip module is provided with a stress-reducing compliant material disposed around the chips prior to molding a polymeric substrate around the chips. Chips having contact pads are placed face down on a layer of adhesive supported by a base. A compliant material is deposited around the chips, and then a mold form is positioned around the chips. Polymeric substrate molding material is added within the mold form, and then the substrate molding material is hardened. A dielectric layer having vias aligned with predetermined ones of the contact pads and having an electrical conductor extending through the vias is situated on the hardened substrate molding material and faces of the chips. A thermal plug may be affixed to the backside of a chip prior to the addition of substrate molding material.

Abstract: Connection elements which, for example, may be used to facilitate interconnection to and stacking of electronic assemblies or may include an elongated conductive core, such as a wire or a hollow tube structure, coated with a layer of elastomeric material containing conductive particle such that the elastomeric material is conductive at least when compressed. The substrates of multi-chip modules (MCMs) have electrical connection sites in the form of metal-lined channels in the substrate edges, and the connection elements are pressed into the channels. Separate compression or clamping elements may be employed to enhance conductivity, as well as to facilitate external connections. The elongated conductive core may take the form of a hollow tube structure which may be expanded under internal pressure to compress the layer of elastomeric material. The compression elements may take the form of printed circuit boards.

Abstract: A method for fabricating a thin film resistor comprises applying a tantalum nitride layer over a dielectric layer, applying a metallization layer over the tantalum nitride layer, and patterning the metallization layer with a first portion of the metallization layer situated apart from a second portion of the metallization layer and both the first and second portions being at least partially situated on the tantalum nitride layer. In one embodiment, after patterning the metallization layer, the resistance value between the first and second portions of the metallization layer is determined and compared to a predetermined resistance value, and at least one of the first and second portions is trimmed to obtain a modified resistance value between the first and second portions that is closer to the predetermined resistance value than the determined resistance value.

Abstract: A method for fabricating a low dielectric constant printed circuit board includes dispersing an additive material in a low dielectric constant porous polymer layer; providing holes through the low dielectric constant porous polymer layer; applying a metallization layer over surfaces of the low dielectric constant porous polymer layer and surfaces of the holes; patterning the metallization layer; and removing the additive material from the low dielectric constant porous polymer layer. The removal of the additive material can be accomplished by sublimation, evaporation, and diffusion.

Abstract: HDI fabrication techniques are employed to form a variety of optical waveguide structures in polymer materials. Adaptive optical connections are formed, taking into account the actual position and orientation of devices which may deviate from the ideal. Structures include solid light-conducting structures, hollow light-conducting structures which are also suitable for conducting cooling fluid, and optical switching devices employing liquid crystal material. A "shrink back" method may be used to form a tunnel in polymer material which is then filled with an uncured polymer material that shrinks upon curing.

Abstract: First and second flexible interconnect structures are provided and each includes a flexible interconnect layer and a chip with a surface having chip pads attached to the flexible interconnect layer. Molding material is inserted between the flexible interconnect layers for encapsulating the respective chips. Vias in the flexible interconnect layers are formed to extend to selected chip pads, and a pattern of electrical conductors is applied which extends over the flexible interconnect layers and into the vias to couple selected ones of the chip pads.

Abstract: A method is provided for the manufacture of precision electronic components such as resistors, inductors, and capacitors on a polymer or ceramic surface. The electronic components can be deposited and trimmed to precise or matched values without having precise depositions of all of the pre-patterned materials. Thin film electronic components are deposited on a surface, parameter values are measured or estimated, a correction offset file is generated, and the components are trimmed using adaptive lithography to a very close tolerance. A computer program can be used to enable the adjustment of electronic components by techniques such as changing the physical length of an inductor coil or resistor lead, or by changing a capacitor plate area.

Abstract: A method for fabricating a thin film resistor comprises applying a tantalum nitride layer over a dielectric layer, applying a metallization layer over the tantalum nitride layer, and patterning the metallization layer with a first portion of the metallization layer situated apart from a second portion of the metallization layer and both the first and second portions being at least partially situated on the tantalum nitride layer. In one embodiment, after patterning the metallization layer, the resistance value between the first and second portions of the metallization layer is determined and compared to a predetermined resistance value, and at least one of the first and second portions is trimmed to obtain a modified resistance value between the first and second portions that is closer to the predetermined resistance value than the determined resistance value.

Abstract: A method for interconnecting at least one semiconductor chip (14 or 36) having chip pads (16 or 38) includes applying a removable polymer layer (22 or 44) over the chip; forming vias (26 or 50) in the polymer layer aligned with predetermined chip pads; depositing a pattern of electrical conductors (28 or 52) over the polymer layer and into the vias; and removing the polymer layer. Prior to applying the polymer layer, the chip can be attached to a substrate by attaching a backside of the chip in a substrate chip well using a high temperature chip attach material (12) or by inserting the chip in a through hole of the substrate and applying a metallization plane (54) supporting the backside of the chip and at least a portion of the substrate.