Abstract: A gas is ionized into a plasma. A compound of a dopant is mixed into the plasma, forming a mixed plasma. Using a semiconductor device fabrication system, a layer of III-V material is exposed to the mixed plasma to dope the layer with the dopant up to a depth in the layer, forming a shallow doped portion of the layer. The depth of the dopant is controlled by a second layer of the dopant formed at the shallow doped portion of the layer. The second layer is exposed to a solution, where the solution is prepared to erode the dopant in the second layer at a first rate. After an elapsed period, the solution is removed from the second layer, wherein the elapsed period is insufficient to erode a total depth of the layer and the shallow doped portion by more than a tolerance erosion amount.

Abstract: A gas is ionized into a plasma. A compound of a dopant is mixed into the plasma, forming a mixed plasma. Using a semiconductor device fabrication system, a layer of III-V material is exposed to the mixed plasma to dope the layer with the dopant up to a depth in the layer, forming a shallow doped portion of the layer. The depth of the dopant is controlled by a second layer of the dopant formed at the shallow doped portion of the layer. The second layer is exposed to a solution, where the solution is prepared to erode the dopant in the second layer at a first rate. After an elapsed period, the solution is removed from the second layer, wherein the elapsed period is insufficient to erode a total depth of the layer and the shallow doped portion by more than a tolerance erosion amount.

Abstract: Integrated circuits including at least two electrically conductive interconnect lines and methods of manufacturing generally include a surface of the integrated circuit. At least two electrically conductive interconnect lines are separated by a space of less than 90 nm and are formed on the surface. Each of the at least two interconnect lines includes a metal cap, a copper conductor having an average grain size greater than a line width of the interconnect. A liner layer is provided, wherein the liner layer and the metal cap encapsulate the copper conductor. A dielectric layer overlaying the at least two electrically conductive interconnect lines and extending along sidewalls thereof is provided, wherein the dielectric layer is configured to provide an airgap between the at least two interconnect lines at the spacing.

Abstract: A phase change memory array and method for fabricating the same. The phase change memory array includes a plurality of bottom electrodes, top electrodes, and memory pillars. Each of the memory pillars includes phase change material surrounded by a dielectric casing. The phase change material is positioned between, and in series circuit with, a respective bottom electrode from the bottom electrodes and a respective top electrode from the top electrodes. A continuous layer of selector material is positioned between the memory pillars and the plurality of bottom electrodes. The selector material is configured to conduct electricity only when a voltage across the selector material exceeds a voltage threshold.

Abstract: A metal structure including a first metal end region, a second metal end region, and an intermediate region between the first metal end region and the second metal end region, wherein the intermediate region comprises a metal nanostructure having a plurality of pores.

Abstract: In one embodiment, a method for hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication includes providing a layer of a dielectric material and etching a trench in the layer of the dielectric material, by applying a mixture of an aggressive dielectric etch gas and a polymerizing etch gas to the layer of the dielectric material. In another embodiment, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices. A pitch of the plurality of conductive lines is approximately twenty-eight nanometers.

Abstract: In one embodiment, a method for hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication includes providing a layer of a dielectric material and etching a trench in the layer of the dielectric material, by applying a mixture of an aggressive dielectric etch gas and a polymerizing etch gas to the layer of the dielectric material. In another embodiment, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices. A pitch of the plurality of conductive lines is approximately twenty-eight nanometers.

Abstract: A technique related to sorting entities is provided. An inlet is configured to receive a fluid, and an outlet is configured to exit the fluid. A nanopillar array, connected to the inlet and the outlet, is configured to allow the fluid to flow from the inlet to the outlet. The nanopillar array includes nanopillars arranged to separate entities by size. The nanopillars are arranged to have a gap separating one nanopillar from another nanopillar. The gap is constructed to be in a nanoscale range.

Abstract: A method for forming an overlap transistor includes forming a gate structure over a III-V material, wet cleaning the III-V material on side regions adjacent to the gate structure and plasma cleaning the III-V material on the side regions adjacent to the gate structure. The III-V material is plasma doped on the side regions adjacent to the gate structure to form plasma doped extension regions that partially extend below the gate structure.

Abstract: An article may include a structure including a patterned metal on a surface of a substrate, the patterned metal including metal features separated by gaps of an average dimension of less than about 1000 nm. A porous low dielectric constant material having a dielectric value of less than about 2.7 substantially occupies all gaps. An interface between the metal features and the porous low dielectric constant material may include less than about 0.1% by volume of voids.

Abstract: The present invention relates generally to the field of microelectronics, and more particularly to a structure and method of forming a biosensor having a nucleotide attracting surface formed to reduce false detection of nucleotides and enabling electrical detection of nucleotides. The biosensor may include an analyte-affinity layer on an upper surface of a substrate. A conductive layer may extend a length of the substrate below and in contact with the analyte-affinity layer. The conductive layer may be electrically connected to one or more transistors. The analyte-affinity layer may have dimensions tailored for a target analyte. A distance between a first analyte-affinity layer and a second analyte-affinity layer may range from approximately 50% of a length of a target analyte to approximately 300% of a length of a target analyte. The analyte-affinity layer may have an upper surface with a diameter ranging from approximately 3 nm to approximately 20 nm.

Abstract: A method, computer program product, and system for identifying a surface area size of a biosensing structure, for use in a biosensor device, based on a plurality of nucleotides structures under test. A first set of properties are determined comprising: reaction coordinate values, and potential of mean force (PMF) values, for the plurality of nucleotide structures based on a first set of testing conditions comprising a first surface area material, a first surface area pattern, and a first surface area size. A second set of properties is determined comprising reaction coordinate values, and PMF values, for the plurality of nucleotide structures based on a second set of testing conditions comprising a second surface area material, a second surface area pattern, a second surface area size, or a combination thereof and a target population of nucleotide structures among the plurality of nucleotide structures are identified.

Abstract: The present invention relates generally to the field of microelectronics, and more particularly to a structure and method of forming a biosensor having a nucleotide attracting surface tailored to reduce false detection of nucleotides and enabling optical detection of nucleotides. The biosensor may include an analyte-affinity layer on an upper surface of a dielectric layer. The analyte-affinity layer may include a plurality of cylindrical gold portions with dimensions tailored for a target analyte. A distance between adjacent portions of the plurality of portions may range from approximately 50% of a length of a target analyte to approximately 300% of a length of a target analyte. The plurality of portions of the analyte-affinity layer have an upper surface with a diameter ranging from approximately 3 nm to approximately 20 nm.

Abstract: Various methods for fabricating a semiconductor device by selective in-situ cleaning of a target surface of a semiconductor substrate by selective dry surface atomic layer etching of the target surface film, selectively removing one or more top layers of atoms from the target surface film of the semiconductor substrate. The selective in-situ cleaning of a target surface can be followed by deposition on the cleaned target surface such as to form a cap layer, a conductive contact layer, or a gate dielectric layer.

Abstract: An article may include a structure including a patterned metal on a surface of a substrate, the patterned metal including metal features separated by gaps of an average dimension of less than about 1000 nm. A porous low dielectric constant material having a dielectric value of less than about 2.7 substantially occupies all gaps. An interface between the metal features and the porous low dielectric constant material may include less than about 0.1% by volume of voids. A method may include depositing a filling material including a silicon-based resin having a molecular weight of less than about 30,000 Da and a porogen having a molecular weight greater than about 400 Da onto a structure comprising a patterned metal. The deposited filling material may be subjected to a first thermal treatment to substantially fill all gaps, and subjected to a second thermal treatment and a UV radiation treatment.

Abstract: A technique related to sorting entities is provided. An inlet is configured to receive a fluid, and an outlet is configured to exit the fluid. A nanopillar array, connected to the inlet and the outlet, is configured to allow the fluid to flow from the inlet to the outlet. The nanopillar array includes nanopillars arranged to separate entities by size. The nanopillars are arranged to have a gap separating one nanopillar from another nanopillar. The gap is constructed to be in a nanoscale range.

Abstract: In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form a plurality of lines for connecting semiconductor devices on the integrated circuit. A large feature area is formed outside of the plurality of conductive lines via a metal fill process using a second conductive metal.

Abstract: In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form a plurality of lines for connecting semiconductor devices on the integrated circuit. A large feature area is formed outside of the plurality of conductive lines via a metal fill process using a second conductive metal.

Abstract: In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form a plurality of lines for connecting semiconductor devices on the integrated circuit. A large feature area is formed outside of the plurality of conductive lines via a metal fill process using a second conductive metal.

Abstract: In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form a plurality of lines for connecting semiconductor devices on the integrated circuit. A large feature area is formed outside of the plurality of conductive lines via a metal fill process using a second conductive metal.