Abstract: An apparatus and system having an optical integrated circuit (referred to herein as an OMTP) configured for power on during discovery and optically communicating with the OMTP reader for the purpose of extracting data.

Abstract: An apparatus and system having an optical integrated circuit (referred to herein as an OMTP) configured for power on during discovery and optically communicating with the OMTP reader for the purpose of extracting data.

Abstract: An apparatus and system having an optical integrated circuit (referred to herein as an OMTP) configured for power on during discovery and optically communicating with the OMTP reader for the purpose of extracting data.

Abstract: A method for stacking integrated circuit substrates and the substrates used therein are disclosed. In the method, an integrated circuit substrate having top and bottom surfaces is provided. The substrate is divided vertically into a plurality of layers including an integrated circuit layer having integrated circuit elements constructed therein and a buffer layer adjacent to the bottom surface. An alignment fiducial mark extending from the top surface of the wafer into the substrate to a depth below that of the circuit layer is constructed. The vias are arranged in a pattern that provides a fiducial mark when viewed from the bottom surface of the substrate. The pattern can be chosen such that it is recognized by a commercial stepper/scanner/contact mask aligner when viewed from said backside of said wafer. After the substrate is thinned, the alignment fiducial mark is then used to position a mask used in subsequent processing.

Abstract: A basic building block for wafer scale stacked integrated circuits is disclosed. The building block includes an integrated circuit device having an integrated circuit substrate having a circuit layer sandwiched between a buffer layer and a dielectric layer. The dielectric layer has a top side and a bottom side, the bottom side being in contact with the circuit layer. The top surface of the dielectric layer includes a plurality of pads. Each pad extends above the top surface by a predetermined distance. The pads have dimensions that reduce irregularities in the top surface of the pads. In addition, the pads are arranged in a manner to promote planarization of the surface of the wafer via CMP.

Abstract: A method for stacking integrated circuit substrates and the substrates used therein are disclosed. In the method, an integrated circuit substrate having top and bottom surfaces is provided. The substrate is divided vertically into a plurality of layers including an integrated circuit layer having integrated circuit elements constructed therein and a buffer layer adjacent to the bottom surface. An alignment fiducial mark extending from the top surface of the wafer into the substrate to a depth below that of the circuit layer is constructed. The vias are arranged in a pattern that provides a fiducial mark when viewed from the bottom surface of the substrate. The pattern can be chosen such that it is recognized by a commercial steeper/scanner/contact mask aligner when viewed from said backside of said wafer. After the substrate is thinned, the alignment fiducial mark is then used to position a mask used in subsequent processing.

Abstract: A method for stacking integrated circuit substrates and the substrates used therein are disclosed. In the method, an integrated circuit substrate having top and bottom surfaces is provided. The substrate is divided vertically into a plurality of layers including an integrated circuit layer having integrated circuit elements constructed therein and a buffer layer adjacent to the bottom surface. An alignment fiducial mark extending from the top surface of the wafer into the substrate to a depth below that of the circuit layer is constructed. The vias are arranged in a pattern that provides a fiducial mark when viewed from the bottom surface of the substrate. The pattern can be chosen such that it is recognized by a commercial stepper/scanner/contact mask aligner when viewed from said backside of said wafer. After the substrate is thinned, the alignment fiducial mark is then used to position a mask used in subsequent processing.

Abstract: A basic building block for wafer scale stacked integrated circuits is disclosed. The building block includes an integrated circuit device having an integrated circuit substrate having a circuit layer sandwiched between a buffer layer and a dielectric layer. The dielectric layer has a top side and a bottom side, the bottom side being in contact with the circuit layer. The top surface of the dielectric layer includes a plurality of pads. Each pad extends above the top surface by a predetermined distance. The pads have dimensions that reduce irregularities in the top surface of the pads. In addition, the pads are arranged in a manner to promote planarization of the surface of the wafer via CMP.

Abstract: A basic building block for wafer scale stacked integrated circuits is disclosed. The building block includes an integrated circuit device having an integrated circuit substrate having a circuit layer sandwiched between a buffer layer and a dielectric layer. The dielectric layer has a top side and a bottom side, the bottom side being in contact with the circuit layer. The top surface of the dielectric layer includes a plurality of pads. Each pad extends above the top surface by a predetermined distance. The pads have dimensions that reduce irregularities in the top surface of the pads. In addition, the pads are arranged in a manner to promote planarization of the surface of the wafer via CMP.

Abstract: A basic building block for wafer scale stacked integrated circuits is disclosed. The building block includes an integrated circuit device having an integrated circuit substrate having a circuit layer sandwiched between a buffer layer and a dielectric layer. The dielectric layer has a top side and a bottom side, the bottom side being in contact with the circuit layer. The top surface of the dielectric layer includes a plurality of pads. Each pad extends above the top surface by a predetermined distance. The pads have dimensions that reduce irregularities in the top surface of the pads. In addition, the pads are arranged in a manner to promote planarization of the surface of the wafer via CMP.

Abstract: A method for stacking integrated circuit substrates and the substrates used therein are disclosed. In the method, an integrated circuit substrate having top and bottom surfaces is provided. The substrate is divided vertically into a plurality of layers including an integrated circuit layer having integrated circuit elements constructed therein and a buffer layer adjacent to the bottom surface. An alignment fiducial mark extending from the top surface of the wafer into the substrate to a depth below that of the circuit layer is constructed. The vias are arranged in a pattern that provides a fiducial mark when viewed from the bottom surface of the substrate. The pattern can be chosen such that it is recognized by a commercial steeper/scanner/contact mask aligner when viewed from said backside of said wafer. After the substrate is thinned, the alignment fiducial mark is then used to position a mask used in subsequent processing.

Abstract: A circuit having an interconnect network and plurality of processing blocks is disclosed. The interconnect network has a plurality of network nodes arranged in a two-dimensional array on a first substrate. Each network node has a plurality of communication ports and is connected to each adjacent network node by a communication bus that connects only those two network nodes and processing blocks adjacent to that communication bus. A programmable switch within each node connects one of the input ports to one of the output ports in response to connection information stored in a memory in that node. Three-dimensional embodiments can be constructed by including a second substrate that overlies the first substrate and includes a second such interconnect network that is connected vertically through one or more nodes. The circuit easily accommodates spare processing blocks that can be substituted for defective blocks by altering the connection information.

Abstract: A circuit having an interconnect network and plurality of processing blocks is disclosed. The interconnect network has a plurality of network nodes arranged in a two-dimensional array on a first substrate. Each network node has a plurality of communication ports and is connected to each adjacent network node by a communication bus that connects only those two network nodes and processing blocks adjacent to that communication bus. A programmable switch within each node connects one of the input ports to one of the output ports in response to connection information stored in a memory in that node. Three-dimensional embodiments can be constructed by including a second substrate that overlies the first substrate and includes a second such interconnect network that is connected vertically through one or more nodes. The circuit easily accommodates spare processing blocks that can be substituted for defective blocks by altering the connection information.

Abstract: An integrated circuit wafer element and an improved method for bonding the same to produce a stacked integrated circuit. Plugs that extend from one surface of the wafer into the wafer are used to provide vertical connections and to bond the wafers together. A stacked integrated circuit is constructed by bonding the front side of a new wafer to a wafer in the stack and then thinning the backside of the new wafer to a thickness that leaves a portion of the plugs extending above the surface of the backside of the thinned wafer. The elevated plug ends can then be used to bond another wafer by bonding to pads on the front side of that wafer. The mating bonding pads can include depressed regions that mate to the elevated plug ends.

Abstract: A memory that stores a plurality of data storage words, each data storage word includes a plurality of data storage cells arranged as a plurality of columns of data storage cells, at least one of the data storage cells storing data specifying a data value having 3 or more states. The memory includes a plurality of data lines, one such data line corresponding to each column of data storage cells. Each data storage cell sets its state or provides a signal representative of its state via the data line connected to that cell in response to control signals. The memory also includes an error encryption circuit for receiving a data word to be stored in the memory and generating therefrom an encrypted data storage word. The encryption circuit divides the encrypted data storage word into a plurality of sub-data storage words.

Abstract: An integrated circuit wafer element and an improved method for bonding the same to produce a stacked integrated circuit. Plugs that extend from one surface of the wafer into the wafer are used to provide vertical connections and to bond the wafers together. A stacked integrated circuit is constructed by bonding the front side of a new wafer to a wafer in the stack and then thinning the backside of the new wafer to a thickness that leaves a portion of the plugs extending above the surface of the backside of the thinned wafer. The elevated plug ends can then be used to bond another wafer by bonding to pads on the front side of that wafer. The mating bonding pads can include depressed regions that mate to the elevated plug ends.

Abstract: An integrated circuit wafer element and an improved method for bonding the same to produce a stacked integrated circuit. Plugs that extend from one surface of the wafer into the wafer are used to provide vertical connections and to bond the wafers together. A stacked integrated circuit is constructed by bonding the front side of a new wafer to a wafer in the stack and then thinning the backside of the new wafer to a thickness that leaves a portion of the plugs extending above the surface of the backside of the thinned wafer. The elevated plug ends can then be used to bond another wafer by bonding to pads on the front side of that wafer. The mating bonding pads can include depressed regions that mate to the elevated plug ends.

Abstract: An integrated circuit wafer element and an improved method for bonding the same to produce a stacked integrated circuit. Plugs that extend from one surface of the wafer into the wafer are used to provide vertical connections and to bond the wafers together. A stacked integrated circuit is constructed by bonding the front side of a new wafer to a wafer in the stack and then thinning the backside of the new wafer to a thickness that leaves a portion of the plugs extending above the surface of the backside of the thinned wafer. The elevated plug ends can then be used to bond another wafer by bonding to pads on the front side of that wafer. The mating bonding pads can include depressed regions that mate to the elevated plug ends.

Abstract: A reconfigurable memory having M bit lines and a plurality of row lines, where M>1. The memory includes an array of memory storage cells, each memory storage cell storing a data value. The data value is read from or into the storage cells by coupling that data value to one of the bit lines in response to a row control signal on one of the row lines. A row select circuit generates the row control signal on one of the row lines in response to a row address being coupled to the row select circuit. The row select circuit includes a memory for storing a mapping of the row addresses to the row lines that determines which of the row lines is selected for each possible value of the row address.

Abstract: A memory organized as a two-dimensional array of data storage cells having a plurality of rows and columns. Each data storage cell has first, second, third, and fourth terminals, each data storage cell sinking a current between the first and second terminals indicative of a charge stored therein when the third terminal is at a first potential. The memory has a plurality of bit lines, one corresponding to each column. The first terminal of each data storage cell in each column is connected to the bit line corresponding to that column when the third terminal is at the first potential and each data storage cell is disconnected from that bit line when the third terminal is at a second potential. The memory also includes a plurality of column select lines and row select lines. There is one column select line corresponding to each column and one additional column select line adjacent to either the first or last column.