Abstract: A multi-level memory in which each storage cell stores multiple bits. The memory includes a plurality of storage words, a data line, a plurality of reference lines, and a read circuit. Each storage word includes a data memory cell and a plurality of reference memory cells. A stored charge determines a conductivity value measurable between the first and second terminals of each memory cell. The read circuit generates a digital value indicative of the value stored in the data memory cell of a storage word that is connected to the data and reference lines by comparing the conductivity of the data line with a continuous conductivity curve determined by the conductivities of the reference lines.

Abstract: A reconfigurable memory having M bit lines and a plurality of row lines, where M>1. The memory includes an array of memory storage cells, each memory storage cell storing a data value. The data value is read from or into the storage cells by coupling that data value to one of the bit lines in response to a row control signal on one of the row lines. A row select circuit generates the row control signal on one of the row lines in response to a row address being coupled to the row select circuit. The row select circuit includes a memory for storing a mapping of the row addresses to the row lines that determines which of the row lines is selected for each possible value of the row address. The memory includes a plurality of sense amplifiers, one such sense amplifier being connected to each of the bit lines for measuring a signal value on that bit line. A controller that is part of the memory tests the memory storage cells both at power up and run time to detect defective memory storage cells.

Abstract: A variable conductance device having a first source region and a first drain region in a semiconductor substrate. A first channel region connects the first source and the first drain regions. A first resistive layer overlies the first channel region and has first and second electrical contacts spaced apart from one another thereon. The conductance of the path between the first source region and the first drain region depends on the current flowing between the first and second electrical contacts. By adding a FET having its gate and source shorted together to the variable conductance device, a device having the current gain characteristics of a bipolar transistor is obtained. The first drain region is connected to the drain of the FET and the source of the FET is connected to the second electrical contact. The precise form of the current transfer function can be altered by connecting a number of variable conductance devices according to the present invention in parallel.

Abstract: An integrated circuit having first and second identical layers of circuitry. Each layer includes a substrate having a plurality of components thereon. Each layer also includes circuit selection circuitry for enabling the integrated circuit components on that layer to perform a predetermined function. The circuit selection circuitry includes a circuit selection terminal for receiving a signal that enables the predetermined function. Each layer also includes N input pads and N output pads, where N>1. The input and output pads are labeled from 1 to N. Each input pad is connected to a corresponding one of the output pads. The connection scheme is chosen such that there is a one-to-one mapping between the input pads and the output pads and no input pad is connected to an output pad on that layer having the same label as the input pad. The circuit selection terminal is connected to a predetermined one of the input pads.

Abstract: A reconfigurable memory having M bit lines and a plurality of row lines, where M>1. The memory includes an array of memory storage cells, each memory storage cell storing a data value. The data value is read from or into the storage cells by coupling that data value to one of the bit lines in response to a row control signal on one of the row lines. A row select circuit generates the row control signal on one of the row lines in response to a row address being coupled to the row select circuit. The row select circuit includes a memory for storing a mapping of the row addresses to the row lines that determines which of the row lines is selected for each possible value of the row address. The memory includes a plurality of sense amplifiers, one such sense amplifier being connected to each of the bit lines for measuring a signal value on that bit line. A controller that is part of the memory tests the memory storage cells both at power up and run time to detect defective memory storage cells.

Abstract: A non-volatile memory based on a unique EEPROM memory. The non-volatile memory includes a plurality of data memory cells, a data programming circuit, and a first data line. Each data memory cell includes an EEPROM cell having a separate programming electrode and first and second isolation transistors. The programming electrode is coupled to the floating gate by a tunneling window. The first isolation transistor connects the EEPROM cell to the first data line. The second isolation transistor connects the programming electrode to the data programming circuit in response to a write enable signal. The data programming circuit programs a selected data memory cell by receiving a data value to be stored in that data memory cell and generating and coupling a programming signal to the second isolation transistors, the programming signal having a duration that is determined by the received data value.

Abstract: A memory constructed from a plurality of data storage words. Each data storage word includes a plurality of data storage cells and a plurality of reference storage cells, each data storage cell and each reference storage cell having at least 4 states. The memory has a plurality of reference lines, one such reference line corresponding to each reference storage cell. The corresponding reference storage cell is connected to that reference line by a gate included in that storage cell. Each reference cell assumes one of the states in response to a signal on the corresponding reference line and a write signal, the state being determined by the signal on the corresponding reference line. The memory also includes a plurality of data lines, one such data line corresponding to each data storage cell, the corresponding data storage cell being connected to that data line by a gate in that storage cell.