Patents by Inventor Robert R. Rogers

Robert R. Rogers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130339707
    Abstract: Execution of instructions in a transactional environment is selectively controlled. A TRANSACTION BEGIN instruction initiates a transaction and includes controls that selectively indicate whether certain types of instructions are permitted to execute within the transaction. The controls include one or more of an allow access register modification control and an allow floating point operation control.
    Type: Application
    Filed: March 7, 2013
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dan F. Greiner, Christian Jacobi, Robert R. Rogers, Timothy J. Slegel
  • Publication number: 20130339328
    Abstract: Execution of instructions in a transactional environment is selectively controlled. A TRANSACTION BEGIN instruction initiates a transaction and includes controls that selectively indicate whether certain types of instructions are permitted to execute within the transaction. The controls include one or more of an allow access register modification control and an allow floating point operation control.
    Type: Application
    Filed: June 15, 2012
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dan F. Greiner, Christian Jacobi, Robert R. Rogers, Timothy J. Slegel
  • Patent number: 8572357
    Abstract: A monitoring facility that is operable in two modes allowing compatibility with prior existing monitoring facilities. In one mode, in response to encountering a monitored event, an interrupt is generated. In another mode, in response to encountering a monitored event, one or more associated counters are incremented without causing an interrupt.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: October 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Dan Greiner, James H. Mulder, Robert R. Rogers, Robert W. StJohn
  • Publication number: 20130185735
    Abstract: A program (e.g., an operating system) is provided a warning that it has a grace period in which to perform a function, such as cleanup (e.g., complete, stop and/or move a dispatchable unit). The program is being warned, in one example, that it is losing access to its shared resources. For instance, in a virtual environment, a guest program is warned that it is about to lose its central processing unit resources, and therefore, it is to perform a function, such as cleanup.
    Type: Application
    Filed: January 18, 2012
    Publication date: July 18, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark S. Farrell, Charles W. Gainey, JR., Jeffrey P. Kubala, James H. Mulder, Bernard Pierce, Robert R. Rogers, Donald W. Schmidt
  • Patent number: 8489867
    Abstract: A monitoring facility that is operable in two modes allowing compatibility with prior existing monitoring facilities. In one mode, in response to encountering a monitored event, an interrupt is generated. In another mode, in response to encountering a monitored event, one or more associated counters are incremented without causing an interrupt.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: July 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: Dan Greiner, James H. Mulder, Robert R. Rogers, Robert W. Stjohn
  • Publication number: 20130014123
    Abstract: An embodiment provides for operating an information processing system. An aspect of the invention includes allocating an execution interval to a first logical processor of a plurality of logical processors of the information processing system. The execution interval is allocated for use by the first logical processor in executing instructions on a physical processor of the information processing system. The first logical processor determines that a resource required for execution by the first logical processor is locked by another one of the other logical processors. An instruction is issued by the first logical processor to determine whether a lock-holding logical processor is currently running. The lock-holding logical processor waits to release the lock if it is currently running. A command is issued by the first logical processor to a super-privileged process for relinquishing the allocated execution interval by the first logical processor if the locking holding processor is not running.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 10, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Greg A. Dyck, Mark S. Farrell, Charles W. Gainey, Jeffrey P. Kubala, Robert R. Rogers, Mark A. Wisniewski
  • Patent number: 8281315
    Abstract: Exemplary embodiments include a system and storage medium for managing computer processing functions in a multi-processor computer environment. The system includes a physical processor, a standard logical processor, an assist logical processor sharing a same logical partition as the standard logical processor, and a single operating system instance associated with the logical partition, the single operating system instance including a switch-to service and a switch-from service. The system also includes a dispatch component managed by the single operating system instance. Upon invoking the switch-to service by standard code, the switch-to service checks to see if an assist logical processor is online and, if so, it updates an integrated assist field of a work element block associated with the task for indicating the task is eligible to be executed on the assist logical processor. The switch-to service also assigns a work queue to the work element block.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: October 2, 2012
    Assignee: International Business Machines Corporation
    Inventors: Donald F. Ault, Jose R. Castano, Jeffrey P. Kubala, Robert J. Maddison, Bernard R. Pierce, Gary S. Puchkoff, Peter J. Relson, Robert R. Rogers, Donald W. Schmidt, Leslie W. Wyman
  • Patent number: 8276155
    Abstract: Exemplary embodiments include a system and storage medium for managing computer processing functions in a multi-processor computer environment. The system includes a physical processor, a standard logical processor, an assist logical processor sharing a same logical partition as the standard logical processor, and a single operating system instance associated with the logical partition, the single operating system instance including a switch-to service and a switch-from service. The system also includes a dispatch component managed by the single operating system instance. Upon invoking the switch-to service by standard code, the switch-to service checks to see if an assist logical processor is online and, if so, it updates an integrated assist field of a work element block associated with the task for indicating the task is eligible to be executed on the assist logical processor. The switch-to service also assigns a work queue to the work element block.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: September 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Donald F. Ault, Jose R. Castano, Jeffrey P. Kubala, Robert J. Maddison, Bernard R. Pierce, Gary S. Puchkoff, Peter J. Relson, Robert R. Rogers, Donald W. Schmidt, Leslie W. Wyman
  • Patent number: 8276151
    Abstract: A method is provided for a first logical processor to determine a running status of a target logical processor of an information processing system. In such method, an instruction is issued by the first logical processor running on the information processing system for determining whether the target logical processor is running. In response to issuing the instruction, a state descriptor belonging to the target logical processor is queried to determine whether the target logical processor is currently running. A result is then returned to the first logical processor, the result indicating whether or not the target logical processor is currently running.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: September 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Greg A. Dyck, Mark S. Farrell, Charles W. Gainey, Jeffrey P. Kubala, Robert R. Rogers, Mark A. Wisniewski
  • Publication number: 20120198216
    Abstract: A monitoring facility that is operable in two modes allowing compatibility with prior existing monitoring facilities. In one mode, in response to encountering a monitored event, an interrupt is generated. In another mode, in response to encountering a monitored event, one or more associated counters are incremented without causing an interrupt.
    Type: Application
    Filed: April 13, 2012
    Publication date: August 2, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dan Greiner, James H. Mulder, Robert R. Rogers, Robert W. Stjohn
  • Publication number: 20110113434
    Abstract: Exemplary embodiments include a system and storage medium for managing computer processing functions in a multi-processor computer environment. The system includes a physical processor, a standard logical processor, an assist logical processor sharing a same logical partition as the standard logical processor, and a single operating system instance associated with the logical partition, the single operating system instance including a switch-to service and a switch-from service. The system also includes a dispatch component managed by the single operating system instance. Upon invoking the switch-to service by standard code, the switch-to service checks to see if an assist logical processor is online and, if so, it updates an integrated assist field of a work element block associated with the task for indicating the task is eligible to be executed on the assist logical processor. The switch-to service also assigns a work queue to the work element block.
    Type: Application
    Filed: January 20, 2011
    Publication date: May 12, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Donald F. Ault, Jose R. Castano, Jeffrey P. Kubala, Robert J. Maddison, Bernard R. Pierce, Gary S. Puchkoff, Peter J. Relson, Robert R. Rogers, Donald W. Schmidt, Leslie W. Wyman
  • Publication number: 20110078421
    Abstract: A monitoring facility that is operable in two modes allowing compatibility with prior existing monitoring facilities. In one mode, in response to encountering a monitored event, an interrupt is generated. In another mode, in response to encountering a monitored event, one or more associated counters are incremented without causing an interrupt.
    Type: Application
    Filed: September 29, 2009
    Publication date: March 31, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dan Greiner, James H. Mulder, Robert R. Rogers, Robert W. Stjohn
  • Patent number: 7657889
    Abstract: A method of searching for work elements for processing in a computing system having a primary queue of work elements and at least one secondary queue of work elements. A numerical priority value is associated with each of the work elements. The method includes setting an initial priority bar and processing work elements from the primary queue until reaching a work element having a priority less than the initial priority bar. A priority bar is set equal to a minimum of a priority limit and a priority on the at least one secondary queue. If the primary queue contains a work element having a priority greater than or equal to the priority bar, then the work element is processed. If the primary queue contains a work element having a priority less than the priority bar, then a work element from the at least one secondary queue is processed.
    Type: Grant
    Filed: April 6, 2004
    Date of Patent: February 2, 2010
    Assignee: International Business Machines Corporation
    Inventors: Bernard R. Pierce, Robert R. Rogers
  • Patent number: 7650469
    Abstract: A method is provided for determining whether a logical processor of an information processing system has access to an address space of the information processing system. An instruction is issued by a first processor, the instruction referencing a target logical processor and a target address space. In response to the instruction, first information is checked to determine whether the target logical processor is running. When it is determined that the target logical processor is not running, second information is checked by a host program to determine whether the target logical processor has access to the target address space.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: January 19, 2010
    Assignee: International Business Machines Corporation
    Inventors: Greg A. Dyck, Charles W. Gainey, Jeffrey P. Kubala, James H. Mulder, Damian L. Osisek, Robert R. Rogers, Mark A. Wisniewski, Leslie W. Wyman
  • Publication number: 20090259875
    Abstract: Two forms of TOD Clock instructions are provided, Store Clock and Store Clock Fast. Execution of the Store Clock Fast instruction may produce a time of day (TOD) result that is exactly the same as a previous TOD result, however execution of Store Clock Fast instructions while the clock is running always produce unique TOD results.
    Type: Application
    Filed: June 22, 2009
    Publication date: October 15, 2009
    Applicant: International Business Machines Corporation
    Inventors: Mark A. Check, Mark S. Farrell, Dan F. Greiner, James H. Mulder, Damian L. Osisek, Robert R. Rogers, Timothy J. Slegel, Ronald M. Smith, SR.
  • Publication number: 20080189714
    Abstract: Exemplary embodiments include a system and storage medium for managing computer processing functions in a multi-processor computer environment. The system includes a physical processor, a standard logical processor, an assist logical processor sharing a same logical partition as the standard logical processor, and a single operating system instance associated with the logical partition, the single operating system instance including a switch-to service and a switch-from service. The system also includes a dispatch component managed by the single operating system instance. Upon invoking the switch-to service by standard code, the switch-to service checks to see if an assist logical processor is online and, if so, it updates an integrated assist field of a work element block associated with the task for indicating the task is eligible to be executed on the assist logical processor. The switch-to service also assigns a work queue to the work element block.
    Type: Application
    Filed: April 3, 2008
    Publication date: August 7, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Donald F. Ault, Jose R. Castano, Jeffrey P. Kubala, Robert J. Maddison, Bernard R. Pierce, Gary S. Puchkoff, Peter J. Relson, Robert R. Rogers, Donald W. Schmidt, Leslie W. Wyman
  • Patent number: 7392524
    Abstract: Exemplary embodiments include a method, system, and storage medium for managing computer processing functions in a multi-processor computer environment that includes a standard logical processor and an assist logical processor, each of which share the same operating system instance within a logical partition. The method includes invoking a switch-to service by standard code. The standard code is running on a standard logical processor and is executing a task. The switch-to service checks to see if an assist logical processor is online, and it if finds one, the switch-to service updates an integrated assist field of a work element block associated with the task and assigns a queue to the work element block. The task is dispatched, in accordance with business rules identified in a system control block, on either of said assist logical processor or said standard logical processor.
    Type: Grant
    Filed: April 6, 2004
    Date of Patent: June 24, 2008
    Assignee: International Business Machines Corporation
    Inventors: Donald F. Ault, Jose R. Castano, Jeffrey P. Kubala, Robert J. Maddison, Bernard R. Pierce, Gary S. Puchkoff, Peter J. Relson, Robert R. Rogers, Donald W. Schmidt, Leslie W. Wyman
  • Publication number: 20080071502
    Abstract: A method is provided for obtaining time-of-day (“TOD”) clock records on an information processing system. In accordance with such method, a first instruction is issued for recording a TOD clock value. In response to issuing the first instruction, a truncated version of a first current TOD clock value is obtained and recorded as a first TOD clock record, the first TOD clock value being a first current TOD clock value produced by a TOD clock running continuously on the information processing system. Thereafter, a second instruction is issued. In response to issuing the second instruction, a truncated version of a second current TOD clock value is obtained and recorded as a second TOD clock record, the second current TOD clock value being produced by the TOD clock, and the second TOD clock record being permitted to have the same value as the first TOD clock record.
    Type: Application
    Filed: September 15, 2006
    Publication date: March 20, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark A. Check, Mark S. Farrell, Dan F. Greiner, James H. Mulder, Damian L. Osisek, Robert R. Rogers, Timothy J. Slegel, Ronald M. Smith, Peter G. Sutton
  • Publication number: 20080059719
    Abstract: A method is provided for determining whether a logical processor of an information processing system has access to an address space of the information processing system. An instruction is issued by a first processor, the instruction referencing a target logical processor and a target address space. In response to the instruction, first information is checked to determine whether the target logical processor is running. When it is determined that the target logical processor is not running, second information is checked by a host program to determine whether the target logical processor has access to the target address space.
    Type: Application
    Filed: September 6, 2006
    Publication date: March 6, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Greg A. Dyck, Charles W. Gainey, Jeffrey P. Kubala, James H. Mulder, Damian L. Osisek, Robert R. Rogers, Mark A. Wisniewski, Leslie W. Wyman
  • Publication number: 20080059778
    Abstract: A method is provided for a first logical processor to determine a running status of a target logical processor of an information processing system. In such method, an instruction is issued by the first logical processor running on the information processing system for determining whether the target logical processor is running. In response to issuing the instruction, a state descriptor belonging to the target logical processor is queried to determine whether the target logical processor is currently running. A result is then returned to the first logical processor, the result indicating whether or not the target logical processor is currently running.
    Type: Application
    Filed: September 6, 2006
    Publication date: March 6, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Greg A. Dyck, Mark S. Farrell, Charles W. Gainey, Jeffrey P. Kubala, Robert R. Rogers, Mark A. Wisniewski