Abstract: Provided are electrical circuits and methods for power factor correction. An example method includes receiving, by converter, an input voltage at a fundamental frequency and generating an output voltage; generating, based on the output voltage, a first measurement signal; subtracting a first reference signal from the first measurement signal to obtain a first error signal; generating an adaptive current sense signal, generating a reference voltage based on the input voltage, subtracting the reference voltage from the current sense signal thus generating a second measurement signal to control the current measurement; subtracting the second measurement signal from the input voltage to obtain a difference signal, wherein the difference signal is largely minimized by removing overtones of the fundamental frequency; generating, based on the difference signal, a second error signal; using a sum of the second error signal as a first order correction to the first error signal to regulate the converter.

Abstract: Provided are electrical circuits and methods for power factor correction. An example method includes receiving, by converter, an input voltage at a fundamental frequency and generating an output voltage; generating, based on the output voltage, a first measurement signal; subtracting a first reference signal from the first measurement signal to obtain a first error signal; generating an adaptive current sense signal, generating a reference voltage based on the input voltage, subtracting the reference voltage from the current sense signal thus generating a second measurement signal to control the current measurement; subtracting the second measurement signal from the input voltage to obtain a difference signal, wherein the difference signal is largely minimized by removing overtones of the fundamental frequency; generating, based on the difference signal, a second error signal; using a sum of the second error signal as a first order correction to the first error signal to regulate the converter.

Abstract: Provided are electrical circuits and methods for power factor correction. An example method includes receiving, by converter, an input voltage at a fundamental frequency and generating an output voltage; generating, based on the output voltage, a first measurement signal; subtracting a first reference signal from the first measurement signal to obtain a first error signal; generating an adaptive current sense signal, generating a reference voltage based on the input voltage, subtracting the reference voltage from the current sense signal thus generating a second measurement signal to control the current measurement; subtracting the second measurement signal from the input voltage to obtain a difference signal, wherein the difference signal is largely minimized by removing overtones of the fundamental frequency; generating, based on the difference signal, a second error signal; using a sum of the second error signal as a first order correction to the first error signal to regulate the converter.

Abstract: Provided are electrical circuits and methods for power factor correction. An example method includes receiving, by converter, an input voltage at a fundamental frequency and generating an output voltage; generating, based on the output voltage, a first measurement signal; subtracting a first reference signal from the first measurement signal to obtain a first error signal; generating an adaptive current sense signal, generating a reference voltage based on the input voltage, subtracting the reference voltage from the current sense signal thus generating a second measurement signal to control the current measurement; subtracting the second measurement signal from the input voltage to obtain a difference signal, wherein the difference signal is largely minimized by removing overtones of the fundamental frequency; generating, based on the difference signal, a second error signal; using a sum of the second error signal as a first order correction to the first error signal to regulate the converter.

Abstract: Provided are electrical circuits and methods for power factor correction. An example method includes receiving, by converter, an input voltage at a fundamental frequency and generating an output voltage; generating, based on the output voltage, a first measurement signal; subtracting a first reference signal from the first measurement signal to obtain a first error signal; generating an adaptive current sense signal, generating a reference voltage based on the input voltage, subtracting the reference voltage from the current sense signal thus generating a second measurement signal to control the current measurement; subtracting the second measurement signal from the input voltage to obtain a difference signal, wherein the difference signal is largely minimized by removing overtones of the fundamental frequency; generating, based on the difference signal, a second error signal; using a sum of the second error signal as a first order correction to the first error signal to regulate the converter.

Abstract: Provided are electrical circuits and methods for power factor correction. An example method includes receiving, by converter, an input voltage at a fundamental frequency and generating an output voltage; generating, based on the output voltage, a first measurement signal; subtracting a first reference signal from the first measurement signal to obtain a first error signal; generating an adaptive current sense signal, generating a reference voltage based on the input voltage, subtracting the reference voltage from the current sense signal thus generating a second measurement signal to control the current measurement; subtracting the second measurement signal from the input voltage to obtain a difference signal, wherein the difference signal is largely minimized by removing overtones of the fundamental frequency; generating, based on the difference signal, a second error signal; using a sum of the second error signal as a first order correction to the first error signal to regulate the converter.

Abstract: The disclosed technology performs power factor correction involving rectifying and adjusting an input power supply signal with a PWM signal. The PWM signal is generated based on a closed feedback signal obtained from a load, as well as adjusted harmonic content retrieved from a sensed input power supply signal. The adjusted harmonic content is produced by extracting a fundamental signal and a plurality of harmonic signals from the sensed input power supply signal, modifying the plurality of harmonic signals by dividing by the fundamental signal, and combining the modified harmonic signals into a duty factor distortion signal. The duty factor distortion signal controls a duty factor of the PWM signal to provide a substantially square wave template. Furthermore, the power factor is increased by forcing the input power supply signal to follow the substantially square wave template.

Abstract: A power factor correction circuit responsive to an input power supply signal at an input supply voltage is described. The circuit includes rectifier circuitry for largely performing full-wave rectification on the input supply signal to produce a full-wave rectified supply signal at a full-wave rectified voltage and a full-wave rectified current susceptible of having at least one overtone of the fundamental supply frequency. The circuit also includes a regulator for regulating the full-wave rectified voltage to produce a regulated power supply voltage with reduced voltage ripple, the regulator operating in buck-boost mode, and control circuitry for measuring at least one such overtone in the full-wave rectified current. The control circuitry also provides the regulator with a primary control signal that causes at least one such overtone to be largely removed from the full-wave rectified current.

Abstract: A power factor correction circuit responsive to an input power supply signal at an input supply voltage is described. The circuit includes rectifier circuitry for largely performing full-wave rectification on the input supply signal to produce a full-wave rectified supply signal at a full-wave rectified voltage and a full-wave rectified current susceptible of having at least one overtone of the fundamental supply frequency. The circuit also includes a regulator for regulating the full-wave rectified voltage to produce a regulated power supply voltage with reduced voltage ripple, the regulator operating in buck-boost mode, and control circuitry for measuring at least one such overtone in the full-wave rectified current. The control circuitry also provides the regulator with a primary control signal that causes at least one such overtone to be largely removed from the full-wave rectified current.

Abstract: A power factor correction circuit (42/44) responsive to an input power supply signal at an input supply voltage (VAC) that varies largely sinusoidally with time at a fundamental supply frequency contains regulator/control circuitry (60, 62, and 64) for measuring and removing overtones (ILDm or IFWRm) in the input supply current (ILD) or in a rectified form (IFWR) of the input supply current. Each overtone is expressible as the product of an amplitude component (Im) and a sinusoidal function (Im sin [(m+1)?ACt]) that varies with time at an integer multiple of the fundamental supply frequency. The regulator/control circuitry measures an overtone by determining the overtone's amplitude component. After generating an adjustment factor (SADJ) largely as the product of that overtone's amplitude component and an associated sinusoidal function, the regulator/control circuitry adjusts the input supply current or its rectified form by an amount corresponding to the adjustment factor for each measured overtone.

Abstract: A power factor correction circuit (42/44) responsive to an input power supply signal at an input supply voltage (VAC) that varies largely sinusoidally with time at a fundamental supply frequency contains regulator/control circuitry (60, 62, and 64) for measuring and removing overtones (ILDm or IFWRm) in the input supply current (ILD) or in a rectified form (IFWR) of the input supply current. Each overtone is expressible as the product of an amplitude component (Im) and a sinusoidal function (Im sin [(m+1)?ACt]) that varies with time at an integer multiple of the fundamental supply frequency. The regulator/control circuitry measures an overtone by determining the overtone's amplitude component. After generating an adjustment factor (SADJ) largely as the product of that overtone's amplitude component and an associated sinusoidal function, the regulator/control circuitry adjusts the input supply current or its rectified form by an amount corresponding to the adjustment factor for each measured overtone.

Abstract: A power factor correction circuit (42/44) responsive to an input power supply signal at an input supply voltage (VAC) that varies largely sinusoidally with time at a fundamental supply frequency contains regulator/control circuitry (60, 62, and 64) for measuring and removing overtones (ILDm or IFWRm) in the input supply current (ILD) or in a rectified form (IFWR) of the input supply current. Each overtone is expressible as the product of an amplitude component (Im) and a sinusoidal function (Im sin [(m+1)?ACt]) that varies with time at an integer multiple of the fundamental supply frequency. The regulator/control circuitry measures an overtone by determining the overtone's amplitude component. After generating an adjustment factor (SADJ) largely as the product of that overtone's amplitude component and an associated sinusoidal function, the regulator/control circuitry adjusts the input supply current or its rectified form by an amount corresponding to the adjustment factor for each measured overtone.

Abstract: A circuit for sensing a voltage across a power switch includes a transmission gate, a low pass filter and a comparator. The power switch is controlled by a control signal for turning the power switch on and off to generate a switching voltage at a first current handling terminal of the power switch. The transmission gate is turned on whenever the power switch is turned on to sample the voltage across the power switch when the power switch is turned on. The sampled voltage is filtered by the low pass filter to remove high frequency transients. Finally, the comparator compares the filtered voltage to a reference voltage. The comparator provides an output signal having a first value when the filtered voltage is less than the reference voltage. The circuit can be used as a load sensing circuit to sense the load condition under which the power switch is being operated.

Abstract: A compensation circuit for introducing a zero in a first circuit being incorporated in a closed loop feedback system includes a first capacitor, an amplifier with capacitive feedback and a second capacitor, connected in series between an input node and a summing node in the first circuit. In one embodiment, the summing node is an intermediate node between two gain stages of a second circuit in the first circuit. The capacitive feedback can be formed by a third capacitor coupled in parallel with one or more of the gain stages in the amplifier. In operation, the capacitance of the second capacitor and an input impedance of the second gain stage of the second circuit introduce a zero in the closed loop feedback system at the third node. The compensation circuit can be applied to a switching regulator controller for adding a zero in the feedback system of a switching regulator.

Abstract: An error amplifier circuit includes a differential amplifier with a cascode gain stage and an amplifier. The differential amplifier receives a first input signal and a second input signal and generates an output signal on an output terminal indicative of the difference between the first input signal and the second input signal. The cascode gain stage is coupled to receive the output signal of the differential amplifier and generates a second output signal. The cascode gain stage is biased by a bias current generated by a current mirror. The amplifier receives the second output signal from the cascode gain stage and generates a third output signal. The cascode gain stage is biased by a control signal for causing said current mirror to generate a bias current having substantially constant magnitude over variations in voltage differences of the first input signal and the second input signal.

Abstract: A compensation circuit for introducing a zero in a first circuit being incorporated in a closed loop feedback system includes a first capacitor, an amplifier with capacitive feedback and a second capacitor, connected in series between an input node and a summing node in the first circuit. In one embodiment, the summing node is an intermediate node between two gain stages of a second circuit in the first circuit. The capacitive feedback can be formed by a third capacitor coupled in parallel with one or more of the gain stages in the amplifier. In operation, the capacitance of the second capacitor and an input impedance of the second gain stage of the second circuit introduce a zero in the closed loop feedback system at the third node. The compensation circuit can be applied to a switching regulator controller for adding a zero in the feedback system of a switching regulator.

Abstract: An error amplifier circuit includes a differential amplifier with a cascade gain stage and an amplifier. The differential amplifier receives a first input signal and a second input signal and generates an output signal on an output terminal indicative of the difference between the first input signal and the second input signal. The cascade gain stage is coupled to receive the output signal of the differential amplifier and generates a second output signal. The cascade gain stage is biased by a bias current generated by a current mirror. The amplifier receives the second output signal from the cascade gain stage and generates a third output signal. The cascade gain stage is biased by a control signal for causing said current mirror to generate a bias current having substantially constant magnitude over variations in voltage differences of the first input signal and the second input signal.

Abstract: A compensation circuit for introducing a zero in a first circuit being incorporated in a closed loop feedback system includes a first capacitor, an amplifier and a second capacitor, connected in series between an input node and a summing node in the first circuit. In one embodiment, the summing node is coupled to a summing circuit disposed between two gain stages of an error amplifier in the first circuit. In another embodiment, the summing node is coupled to the output node of the error amplifier. The amplifier amplifies the capacitance of the second capacitor to introduce a zero in the first circuit having effectiveness over a wide frequency range. The compensation circuit can be applied to a switching regulator controller for adding an effective zero in the feedback system of a switching regulator for compensating a double-pole introduced by a LC filter circuit in the switching regulator feedback system.

Abstract: A compensation circuit for introducing a zero in a first circuit being incorporated in a closed loop feedback system includes a first capacitor, an amplifier and a second capacitor, connected in series between an input node and a summing node in the first circuit. In one embodiment, the summing node is coupled to a summing circuit disposed between two gain stages of an error amplifier in the first circuit. In another embodiment, the summing node is coupled to the output node of the error amplifier. The amplifier amplifies the capacitance of the second capacitor to introduce a zero in the first circuit having effectiveness over a wide frequency range. The compensation circuit can be applied to a switching regulator controller for adding an effective zero in the feedback system of a switching regulator for compensating a double-pole introduced by a LC filter circuit in the switching regulator feedback system.

Abstract: An integrated circuit fabrication process includes a selective substrate implant process to effectively decouple a first power supply connection from a second power supply connection while providing immunity against parasitic effects. In one embodiment, the selective substrate implant process forms heavily doped p-type regions only under P-wells in which noise producing circuitry are built. The noisy ground connection for these P-wells are decoupled from the quiet ground connection for others P-wells not connected to any heavily doped regions and in which noise sensitive circuitry are built. The selective substrate implant process of the present invention has particular applications in forming CMOS analog integrated circuits where it is important to decouple the analog ground for sensitive analog circuitry from the often noisy digital grounds of the digital and power switching circuitry.