Patents by Inventor Robert W. Faber
Robert W. Faber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10438658Abstract: Provided is a non-volatile memory device comprising a plurality of memory cells and memory control logic that when executed performs operations comprising initiating a refresh operation; in response to the refresh operation, performing a read of the memory cells to read values of the memory cells; determining whether the read memory cells have a first value or a second value; and for the memory cells determined to have the first value, rewriting the determined first value to the memory cell, wherein the rewriting operation is not performed with respect to memory cells determined to have the second value.Type: GrantFiled: December 26, 2014Date of Patent: October 8, 2019Assignee: INTEL CORPORATIONInventors: Ningde Xie, Robert W. Faber
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Patent number: 10025737Abstract: A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.Type: GrantFiled: June 4, 2015Date of Patent: July 17, 2018Assignee: Intel CorporationInventors: Shekoufeh Qawami, Rajesh Sundaram, David J. Zimmerman, Robert W. Faber
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Patent number: 9971685Abstract: A first set representing a first plurality of physical block addresses of a non-volatile memory and a second set representing a second plurality of physical block addresses of the non-volatile memory may be identified. In response to a request to perform a wear leveling operation, first data from a first physical block address of the first set may be swapped with second data from a first physical block address of the second set. A second physical block address of the first set that is adjacent to the first physical block address of the first set may be identified. Third data from the second physical block address of the first set may be swapped with fourth data from a second physical block address of the second set that is adjacent to the first physical block of the second set.Type: GrantFiled: April 1, 2016Date of Patent: May 15, 2018Assignee: Intel CorporationInventors: Jason A. Gayman, Robert W. Faber
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Publication number: 20170286293Abstract: A first set representing a first plurality of physical block addresses of a non-volatile memory and a second set representing a second plurality of physical block addresses of the non-volatile memory may be identified. In response to a request to perform a wear leveling operation, first data from a first physical block address of the first set may be swapped with second data from a first physical block address of the second set. A second physical block address of the first set that is adjacent to the first physical block address of the first set may be identified. Third data from the second physical block address of the first set may be swapped with fourth data from a second physical block address of the second set that is adjacent to the first physical block of the second set.Type: ApplicationFiled: April 1, 2016Publication date: October 5, 2017Inventors: Jason A. Gayman, Robert W. Faber
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Patent number: 9501405Abstract: Systems and methods of memory cell wear management that can achieve a more uniform distribution of write cycles across a memory cell address space. The systems and methods allow physical addresses of memory cells subjected to a high number of write cycles to be swapped with physical addresses of memory cells subjected to a lower number of write cycles. The physical address of a group of memory cells is a “hot address” if the write cycle count for that memory cell group exceeds a specified threshold. If the write cycle count for a group of memory cells does not exceed the specified threshold, then the physical address of that memory cell group is a “cold address”. The systems and methods allow the specified threshold of write cycle counts to be dynamically incremented to assure that cold addresses are available for swapping with hot addresses in the memory cell address space.Type: GrantFiled: May 6, 2015Date of Patent: November 22, 2016Assignee: Intel CorporationInventors: Prashant S. Damle, Robert W. Faber, Ningde Xie
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Publication number: 20160189774Abstract: Provided is a non-volatile memory device comprising a plurality of memory cells and memory control logic that when executed performs operations comprising initiating a refresh operation; in response to the refresh operation, performing a read of the memory cells to read values of the memory cells; determining whether the read memory cells have a first value or a second value; and for the memory cells determined to have the first value, rewriting the determined first value to the memory cell, wherein the rewriting operation is not performed with respect to memory cells determined to have the second value.Type: ApplicationFiled: December 26, 2014Publication date: June 30, 2016Inventors: Ningde XIE, Robert W. FABER
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Patent number: 9257175Abstract: Embodiments including systems, methods, and apparatuses associated with refreshing memory cells are disclosed herein. In embodiments, a memory controller may be configured to perform a read operation on one or more memory cells in a cross-point non-volatile memory such as a phase change memory (PCM). The one or more memory cells may have voltage values respectively set to a first threshold voltage or a second threshold voltage. Based on the read, the memory controller may identify the memory cells in the cross-point non-volatile memory that are set to the second threshold voltage, and refresh the voltage values of those cells without altering the voltage values of the memory cells in the cross-point non-volatile memory that are set to the first threshold voltage. Other embodiments may be described or claimed.Type: GrantFiled: September 26, 2013Date of Patent: February 9, 2016Assignee: INTEL CORPORATIONInventors: Kiran Pangal, Raj K. Ramanujan, Robert W. Faber, Rajesh Sundaram
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Patent number: 9202548Abstract: An apparatus is described having invert determination logic circuitry to determine if a read data path that transports data read from a PCMS memory device is to be inverted or not inverted as a function of whether information represented by the data was last written in an inverted or non inverted logical state to the PCMS memory device during a refresh of said PCMS memory device.Type: GrantFiled: December 22, 2011Date of Patent: December 1, 2015Assignee: Intel CorporationInventor: Robert W. Faber
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Publication number: 20150309926Abstract: Systems and methods of memory cell wear management that can achieve a more uniform distribution of write cycles across a memory cell address space. The systems and methods allow physical addresses of memory cells subjected to a high number of write cycles to be swapped with physical addresses of memory cells subjected to a lower number of write cycles. The physical address of a group of memory cells is a “hot address” if the write cycle count for that memory cell group exceeds a specified threshold. If the write cycle count for a group of memory cells does not exceed the specified threshold, then the physical address of that memory cell group is a “cold address”. The systems and methods allow the specified threshold of write cycle counts to be dynamically incremented to assure that cold addresses are available for swapping with hot addresses in the memory cell address space.Type: ApplicationFiled: May 6, 2015Publication date: October 29, 2015Inventors: Prashant S. Damle, Robert W. Faber, Ningde Xie
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Publication number: 20150269100Abstract: A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.Type: ApplicationFiled: June 4, 2015Publication date: September 24, 2015Inventors: Shekoufeh Qawami, Rajesh Sundaram, David J. Zimmerman, Robert W. Faber
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Patent number: 9141536Abstract: Embodiments describe methods, apparatus, and system configurations for providing targeted wear management in nonvolatile memory. Specifically, embodiments may include a memory controller to receive a memory access request directed to a storage unit of the nonvolatile memory. The memory controller may access metadata in the storage unit and determine whether to perform a memory access in accordance with the memory access request based on the state information. Other embodiments may be described or claimed.Type: GrantFiled: November 4, 2011Date of Patent: September 22, 2015Assignee: Intel CorporationInventor: Robert W. Faber
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Patent number: 9064560Abstract: A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.Type: GrantFiled: November 8, 2013Date of Patent: June 23, 2015Assignee: Intel CorporationInventors: Shekoufeh Qawami, Rajesh Sundaram, David J. Zimmerman, Robert W. Faber
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Patent number: 9032137Abstract: Systems and methods of memory cell wear management that can achieve a more uniform distribution of write cycles across a memory cell address space. The systems and methods allow physical addresses of memory cells subjected to a high number of write cycles to be swapped with physical addresses of memory cells subjected to a lower number of write cycles. The physical address of a group of memory cells is a “hot address” if the write cycle count for that memory cell group exceeds a specified threshold. If the write cycle count for a group of memory cells does not exceed the specified threshold, then the physical address of that memory cell group is a “cold address”. The systems and methods allow the specified threshold of write cycle counts to be dynamically incremented to assure that cold addresses are available for swapping with hot addresses in the memory cell address space.Type: GrantFiled: November 21, 2012Date of Patent: May 12, 2015Assignee: Intel CorporationInventors: Prashant S. Damle, Robert W. Faber, Ningde Xie
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Publication number: 20150089120Abstract: Embodiments including systems, methods, and apparatuses associated with refreshing memory cells are disclosed herein. In embodiments, a memory controller may be configured to perform a read operation on one or more memory cells in a cross-point non-volatile memory such as a phase change memory (PCM). The one or more memory cells may have voltage values respectively set to a first threshold voltage or a second threshold voltage. Based on the read, the memory controller may identify the memory cells in the cross-point non-volatile memory that are set to the second threshold voltage, and refresh the voltage values of those cells without altering the voltage values of the memory cells in the cross-point non-volatile memory that are set to the first threshold voltage. Other embodiments may be described or claimed.Type: ApplicationFiled: September 26, 2013Publication date: March 26, 2015Inventors: Kiran Pangal, Raj K. Ramanujan, Robert W. Faber, Rajesh Sundaram
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Publication number: 20140317337Abstract: Methods and apparatus related to management and/or support of metadata for PCMS (Phase Change Memory with Switch) devices are described. In one embodiment, a PCMS controller allows access to a PCMS device based on metadata. The metadata may be used to provide efficiency, endurance, error correction, etc. as discussed in the disclosure. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: December 30, 2011Publication date: October 23, 2014Inventors: Leena K. Puthiyedath, Marc T. Jones, R. Scott Tetrick, Robert J. Royer, Jr., Raj K. Ramanujan, Glenn J. Hinton, Blaise Fanning, Robert S. Gittins, Mark A. Schmisseur, Frank T. Hady, Robert W. Faber
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Publication number: 20140204663Abstract: An apparatus is described having invert determination logic circuitry to determine if a read data path that transports data read from a PCMS memory device is to be inverted or not inverted as a function of whether information represented by the data was last written in an inverted or non inverted logical state to the PCMS memory device during a refresh of said PCMS memory device.Type: ApplicationFiled: December 22, 2011Publication date: July 24, 2014Inventor: Robert W. Faber
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Publication number: 20140143474Abstract: Systems and methods of memory cell wear management that can achieve a more uniform distribution of write cycles across a memory cell address space. The systems and methods allow physical addresses of memory cells subjected to a high number of write cycles to be swapped with physical addresses of memory cells subjected to a lower number of write cycles. The physical address of a group of memory cells is a “hot address” if the write cycle count for that memory cell group exceeds a specified threshold. If the write cycle count for a group of memory cells does not exceed the specified threshold, then the physical address of that memory cell group is a “cold address”. The systems and methods allow the specified threshold of write cycle counts to be dynamically incremented to assure that cold addresses are available for swapping with hot addresses in the memory cell address space.Type: ApplicationFiled: November 21, 2012Publication date: May 22, 2014Inventors: Prashant S. Damle, Robert W. Faber, Ningde Xie
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Publication number: 20140075107Abstract: A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.Type: ApplicationFiled: November 8, 2013Publication date: March 13, 2014Inventors: Shekoufeh Qawami, Rajesh Sundaram, David J. Zimmerman, Robert W. Faber
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Patent number: 8607089Abstract: A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.Type: GrantFiled: May 19, 2011Date of Patent: December 10, 2013Assignee: Intel CorporationInventors: Shekoufeh Qawami, Rajesh Sundaram, David J. Zimmerman, Robert W. Faber
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Patent number: 8595597Abstract: Embodiments of the invention describe methods, systems and apparatuses to improve solid state device (SSD) write speed by efficiently utilizing error correction code executed for the device. SSDs may be comprised of several NAND memory devices. It is understood that such devices tend to have a raw bit error rate (RBER) that is related to the program/erase cycle count for the device. Embodiments of the invention efficiently use system ECC by changing the operating conditions of the SSD to better utilize the robustness of the implemented ECC algorithm. For example, embodiments of the invention may alter the programming voltage supplied to an SSD to increase write speed; such an increase may increase the RBER of the device, but will not affect the accuracy of such operations due to the ECC that is provisioned for end of life storage fidelity (i.e., the RBER that will occur at the end of life).Type: GrantFiled: March 3, 2011Date of Patent: November 26, 2013Assignee: Intel CorporationInventors: Ningde Xie, Matthew Goldman, Jawad B. Khan, Robert W. Faber