Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing targeted wear management in nonvolatile memory.

Abstract: Techniques for determining an identifier for a volume of memory in a memory device of a computer system. In an embodiment, the memory device detects an indication of an initialization event of the computer system and receives command information after the detecting of the indication. In certain embodiments, the memory device stores an identifier value for association with the volume of memory, wherein the storing is based on whether the received command information specifies that the volume of memory is to be assigned an identifier.

Abstract: A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.

Abstract: Techniques to recover data from an indirected non-volatile memory system after unexpected power failure, as, e.g., NAND memory in electronic devices are disclosed.

Abstract: Embodiments of the invention describe methods, systems and apparatuses to improve solid state device (SSD) write speed by efficiently utilizing error correction code executed for the device. SSDs may be comprised of several NAND memory devices. It is understood that such devices tend to have a raw bit error rate (RBER) that is related to the program/erase cycle count for the device. Embodiments of the invention efficiently use system ECC by changing the operating conditions of the SSD to better utilize the robustness of the implemented ECC algorithm. For example, embodiments of the invention may alter the programming voltage supplied to an SSD to increase write speed; such an increase may increase the RBER of the device, but will not affect the accuracy of such operations due to the ECC that is provisioned for end of life storage fidelity (i.e., the RBER that will occur at the end of life).

Abstract: Techniques to recover data from an indirected non-volatile memory system after unexpected power failure, as, e.g., NAND memory in electronic devices are disclosed.

Abstract: Techniques to recover data from an indirected non-volatile memory system after unexpected power failure, as, e.g., NAND memory in electronic devices are disclosed.

Abstract: A technique includes performing a plurality of write operations to store data in different physical memory locations. Each of the physical memory locations are associated with a logical address that is shared in common among the physical addresses. The technique includes storing sequence information in the physical memory locations to indicate which one of the write operations occurred last.

Abstract: The write disturb that occurs in polymer memories may be reduced by writing back data after a read in a fashion which offsets any effect on the polarity of bits in bit lines associated with the addressed bit. For example, each time the data is written back, its polarity may be alternately changed. In another embodiment, the polarity may be randomly changed.

Abstract: Techniques to manage various errors in memory such as, e.g., NAND memory in electronic devices are disclosed. In some embodiments, erase, read, and program error handling errors are managed.

Abstract: In one embodiment, the present invention includes a method for maintaining a sequence of writes into a disk cache, where the writes correspond to disk write requests stored in the disk cache, and ordering cache writes from the disk cache to a disk drive according to the sequence of writes. In this way, write ordering from an operating system to a disk subsystem is maintained. Other embodiments are described and claimed.

Abstract: In some embodiments, after a hold off time following issuance of a memory command has elapsed, a status read operation is performed to determine a status of the memory command. In some embodiments, if the memory command has not yet completed, a polling interval is used to perform a status read operation to determine the status of the memory command after the polling interval has expired, and repeating the process until the memory command has been completed. Other embodiments are described and claimed.

Abstract: Techniques to recover data from an indirected non-volatile memory system after unexpected power failure, as, e.g., NAND memory in electronic devices are disclosed.

Abstract: An apparatus and method to reduce the initialization time of a system is disclosed. In one embodiment, upon a cache line update, metadata associated with the cache line is stored in a distributed format in non-volatile memory with its associated cache line. Upon indication of an expected shut down, metadata is copied from volatile memory and stored in non-volatile memory in a packed format. In the packed format, multiple metadata associated with multiple cache lines are stored together in, for example, a single memory block. Thus, upon system power up, if the system was shut down in an expected manner, metadata may be restored in volatile memory from the metadata stored in the packed format, with a significantly reduced boot time over restoring metadata from the metadata stored in the distributed format.

Abstract: Write operations store data in different physical memory locations. Each of the physical memory locations are associated with a logical address that is shared in common among the physical addresses. Sequence information stored in the physical memory location indicates which one of the write operations occurred last. The available erased memory location can be split into a list of erased memory locations available to be used and a list of erased memory locations not available to be used. Then, on a failure, only the list of erased memory locations available to be used needs to be analyzed to reconstruct the consumption states of memory locations.

Abstract: A video source device includes a cipher unit. The video source device uses the cipher unit to generate cipher bits for ciphering video to be transmitted to protect the video from unauthorized copying. The video source device authenticates video receiving devices using a symmetric ciphering/deciphering process that requires the video source device to generate and provide the video receiving device with a pseudo random number as the seed/basis number for the symmetric ciphering/deciphering process. The video source device is further provided with a state machine that controls the cipher unit to generate the required pseudo random number for the video source devices, thereby eliminating the need of having to provide separate circuitry to generate the required pseudo random numbers.

Abstract: A host controller interface to manage the complexity of accessing mass storage that takes into account the special handling needs of various memory technologies such as polymer memories.

Abstract: The write disturb that occurs in polymer memories may be reduced by writing back data after a read in a fashion which offsets any effect on the polarity of bits in bit lines associated with the addressed bit. For example, each time the data is written back, its polarity may be alternately changed. In another embodiment, the polarity may be randomly changed.

Abstract: One aspect of the invention provides a novel scheme to preserve the failure state of a memory location. According to one embodiment, the data is read from a memory location in a read-destructive memory device. If the data is found to be valid (uncorrupted) it is written back to the memory location from where it was read in order to preserve it. If the data is found to be invalid (corrupted) then a failure codeword is written in the memory location to indicate a failure of the memory location. The failure codeword may be preselected or dynamically calculated so that it has a mathematical distance greater than all correctable data patterns.

Abstract: A method and apparatus for determining the scope of a content domain for ensuring that a content stream is not re-routed to an unauthorized display device. The apparatus includes a content source device, which supports multiple display outputs coupled to one or more content sink devices. A content source application generates and provides a content stream to a hardware interface which securely transmits the content stream to a protected content sink device using a content protection protocol. The content source application utilizes certain status information to ensure that the content stream is not re-routed to an unprotected or unapproved content sink device. The source application requests the updated session identification code from the transmitter/codec unit using the content protection protocol which is compared against the expected session identification code to ensure that the content display stream has not been re-routed to an unprotected content sink device.