Abstract: Technologies are generally described to determine a download throughput of a wireless connection in an environment hosting multiple wired and wireless connections. According to some examples, a compound probe may be transmitted from a source to a wireless destination. Another compound probe may also be transmitted from the source to the wireless destination. The compound probes may include multiple packets without any dispersion gap. Next, an average intra-packet gap (AIPG) and a minimum intra-packet gap (MIPG) may be determined from the first compound probe. Furthermore, another MIPG may be determined from the later compound probe. The download throughput from the source to the wireless destination may be computed from the AIPG and the MIPGs.

Abstract: An AC-AC converter device includes first and second AC input terminals and first and second AC output terminals. An input device is connected between an input node, a common node, a positive DC terminal and a negative DC terminal, wherein the input node is connected to the first AC input terminal via a first input inductor. An output device is connected between an output node, the positive DC terminal and the negative DC terminal, wherein the output node is connected to the first AC output terminal via an output inductor. A common device is connected between the common node, the positive DC terminal and the negative DC terminal, where the common node is connected to the second AC input terminal via a common inductor. A control device is provided for controlling the switches of the output device and the common device.

Abstract: Technologies are generally described for measuring packet processing time of a remotely connected host device. According to some examples, link capacity may be measured to estimate the packet processing time (PPT). The capacity of the link connected to a host may be measured through active probing with the hosts time-stamping each probing packet after receiving it. Thus, PPT information may be included in the packet receiving process and the processes that the packet undergoes defined by the nature of different computing applications, time-stamping a packet is an example of a process that involves processing time.

Abstract: Examples are disclosed for forwarding cells of partitioned data through a three-stage memory-memory-memory (MMM) input-queued Clos-network (IQC) packet switch. In some examples, each module of the three-stage MMM IQC packet switch includes a virtual queue and a manager that are configured in cooperation with one another to forward a cell from among cells of partitioned data through at least a portion of the switch. The cells of partitioned data may have been partitioned and stored at an input port for the switch and have a destination of an output port for the switch.

Abstract: Methods and apparatus for packetized energy distribution are provided. A data and power delivery network, called a digital grid, is provided to facilitate delivery of power upon request. Energy bits (quanta) serve as a means to deliver energy as well as coding. Voltage pulses of varying time scales are used for coding and current levels help to accurately meet customer's demand. Energy is sent as packets (a combination of energy bits), and specific energy packets are addressed to specific customers permitting accurate monitoring and distribution of electrical energy.

Abstract: A Clos-network packet switching system may include input modules coupled to a virtual output queue, central modules coupled to the input modules, and output modules coupled to the central modules, each output module having a plurality of cross-point buffers for storing a packet and one or more output ports for outputting the packet.

Abstract: Multicast traffic is expected to increase in packet networks, and therefore in switches and routers, by including broadcast and multimedia-on-demand services. Combined input-crosspoint buffered (CICB) switches can provide high performance under uniform multicast traffic. However this is often at the expense of N2 crosspoint buffers. An output-based shared-memory crosspoint-buffered (O-SMCB) packet switch is used where the crosspoint buffers are shared by two outputs and use no speedup. An embodiment of the proposed switch provides high performance under admissible uniform and non-uniform multicast traffic models while using 50% of the memory used in CICB switches that has dedicated buffers. Furthermore, the O-SMCB switch provides higher throughput than an existing SMCB switch where the buffers are shared by inputs.

Abstract: Technologies are generally described to determine a download throughput of a wireless connection in an environment hosting multiple wired and wireless connections. According to some examples, a compound probe may be transmitted from a source to a wireless destination. Another compound probe may also be transmitted from the source to the wireless destination. The compound probes may include multiple packets without any dispersion gap. Next, an average intra-packet gap (AIPG) and a minimum intra-packet gap (MIPG) may be determined from the first compound probe. Furthermore, another MIPG may be determined from the later compound probe. The download throughput from the source to the wireless destination may be computed from the AIPG and the MIPGs.

Abstract: Examples are disclosed for forwarding cells of partitioned data through a three-stage memory-memory-memory (MMM) input-queued Clos-network (IQC) packet switch. In some examples, each module of the three-stage MMM IQC packet switch includes a virtual queue and a manager that are configured in cooperation with one another to forward a cell from among cells of partitioned data through at least a portion of the switch. The cells of partitioned data may have been partitioned and stored at an input port for the switch and have a destination of an output port for the switch.

Abstract: Technologies are generally described for measuring clock skew between two remote hosts connected through a computer network. According to some examples, pairs of probe packets, also referred to as a compound probe, may be transmitted over an end-to-end path in both directions (forward and reverse paths) to measure a gap value at the end nodes for clock skew estimation. Compound probes may arrive at the end nodes with a zero dispersion gap (no separation) and the gap values along the forward and reverse paths may be determined by a capacity of the links connected to the end nodes added to the clock speeds of the measuring nodes upon arriving at the end nodes. The link capacity is a constant network parameter. Thus, the ratio of the measured gap values may provide an estimate of clock speed discrepancy between the end nodes.

Abstract: Technologies are generally described for measuring packet processing time of a remotely connected host device. According to some examples, link capacity may be measured to estimate the packet processing time (PPT). The capacity of the link connected to a host may be measured through active probing with the hosts time-stamping each probing packet after receiving it. Thus, PPT information may be included in the packet receiving process and the processes that the packet undergoes defined by the nature of different computing applications, time-stamping a packet is an example of a process that involves processing time.

Abstract: Examples are disclosed for forwarding cells of partitioned data through a three-stage memory-memory-memory (MMM) input-queued Clos-network (IQC) packet switch. In some examples, each module of the three-stage MMM IQC packet switch includes a virtual queue and a manager that are configured in cooperation with one another to forward a cell from among cells of partitioned data through at least a portion of the switch. The cells of partitioned data may have been partitioned and stored at an input port for the switch and have a destination of an output port for the switch.

Abstract: The invention relates to a method for controlling a series resonant DC/DC converter. The method comprises the steps of: defining a switching period TP having a first half period TA and a second half period TB and defining a subsequent switching period TP+1 after the switching period TP. In a next step, a first set (S1sc1; S1sc1, S4sc1) of switches of a first switching circuit (SC1) is controlled to be ON from the beginning Tstart of the first half period TA minus a time interval ?TAE1, where the time interval ?TAE1 is provided at the end of the first half period TA and a second set (S2sc1; S2sc1, S3sc1) of switches of the first switching circuit (SC1) is controlled to be ON from the beginning Tcenter of the second half period TB minus a time interval ?TBE1, where the time interval ?TBE1 is provided at the end of the second half period TB.

Abstract: The invention relates to a method for controlling a series resonant DC/DC converter. The method comprises the steps of: defining a switching period TP having a first half period TA and a second half period TB and defining a subsequent switching period TP+1 after the switching period TP. In a next step, a first set (S1sc1; S1sc1, S4sc1) of switches of a first switching circuit (SC1) is controlled to be ON from the beginning Tstart of the first half period TA minus a time interval ?TAE1, where the time interval ?TAE1 is provided at the end of the first half period TA and a second set (S2sc1; S2sc1, S3sc1) of switches of the first switching circuit (SC1) is controlled to be ON from the beginning Tcenter of the second half period TB minus a time interval ?TBE1, where the time interval ?TBE1 is provided at the end of the second half period TB.

Abstract: Techniques are generally disclosed for disseminating link state information to one or more nodes of a network of nodes, the network of nodes interconnected via a plurality of communication channels.

Abstract: Examples of are disclosed for configuring one or more routes through a three-stage Clos-network packet switch.

Abstract: Examples are disclosed for forwarding data partitioned into one or more cells through at least a portion of a three-stage memory-memory-memory (MMM) input-queued Clos-network (IQC) packet switch. In some examples, each module of the three-stage MMM IQC packet switch includes a virtual queue and a manager that are configured in cooperation with one another to forward cells through at least a portion of the switch. The cells may have been partitioned and stored at an input port for the switch and destined for an output port for the switch.

Abstract: The present invention relates to a device arranged for converting an AC input voltage to a DC output voltage, comprising a bridgeless boost converter; and a surge protection system. The surge protection system comprises a first protection diode (Dprot1), where the anode is connected to a first AC input terminal and the cathode is connected to a positive boost output terminal (Obp); a second protection diode (Dprot2), where the anode is connected to a negative boost output terminal (Obn) and the cathode is connected to the first AC input terminal; a third protection diode (Dprot3), where the anode is connected to a second AC input terminal and the cathode is connected to the positive boost output terminal (Obp); and a fourth protection diode (Dprot4), where the anode is connected to the negative boost output terminal (Obn) and the cathode is connected to the second AC input terminal.

Abstract: A Pipelined-based Maximal-sized Matching (PMM) scheduling approach for input-buffered switches relaxes the timing constraint for arbitration with a maximal matching scheme. In the PMM approach, arbitration may operate in a pipelined manner. Each subscheduler is allowed to take more than one time slot for its matching. Every time slot, one of them provides the matching result. The subscheduler can adopt a pre-existing efficient maximal matching algorithm such as iSLIP and DRRM. PMM maximizes the efficiency of the adopted arbitration scheme by allowing sufficient time for a number of iterations. PMM preserves 100% throughput under uniform traffic and fairness for best-effort traffic.

Abstract: A pipeline-based matching scheduling approach for input-buffered switches relaxes the timing constraint for arbitration with matching schemes, such as CRRD and CMSD. In the new approach, arbitration may operate in a pipelined manner. Each sub-scheduler is allowed to take more than one time slot for its matching. Every time slot, one of them provides a matching result(s). The sub-scheduler can use a matching scheme such as CRRD and CMSD.