Abstract: Techniques are generally disclosed for disseminating link state information to one or more nodes of a network of nodes, the network of nodes interconnected via a plurality of communication channels.

Abstract: Examples are disclosed for forwarding cells of partitioned data through a three-stage memory-memory-memory (MMM) input-queued Clos-network (IQC) packet switch. In some examples, each module of the three-stage MMM IQC packet switch includes a virtual queue and a manager that are configured in cooperation with one another to forward a cell from among cells of partitioned data through at least a portion of the switch. The cells of partitioned data may have been partitioned and stored at an input port for the switch and have a destination of an output port for the switch.

Abstract: Examples are disclosed for forwarding data partitioned into one or more cells through at least a portion of a three-stage memory-memory-memory (MMM) input-queued Clos-network (IQC) packet switch. In some examples, each module of the three-stage MMM IQC packet switch includes a virtual queue and a manager that are configured in cooperation with one another to forward cells through at least a portion of the switch. The cells may have been partitioned and stored at an input port for the switch and destined for an output port for the switch.

Abstract: Examples of are disclosed for configuring one or more routes through a three-stage Clos-network packet switch.

Abstract: A configuration scheme for IQC switches that hierarchizes the matching process reduces configuration complexity by performing routing first and port matching afterwards in a three-stage Clos-network switch. This scheme applies the reduction concept of Clos networks to the matching process. This, in turn, results in a feasible size of schedulers for up to Exabit-capacity switches, an independent configuration of the middle stage modules from port matches, a reduction of the matching communication overhead between different stages, and a release of the switching function to the last-stage modules in a three-stage switch. The switching performance of the proposed approach using weight-based and weightless selection schemes is high under uniform and non-uniform traffic. The number of stages of a Clos-network switch can be reduced to two.

Abstract: The present invention relates to a device arranged for converting an AC input voltage to a DC output voltage, comprising a bridgeless boost converter; and a surge protection system. The surge protection system comprises a first protection diode (Dprot1), where the anode is connected to a first AC input terminal and the cathode is connected to a positive boost output terminal (Obp); a second protection diode (Dprot2), where the anode is connected to a negative boost output terminal (Obn) and the cathode is connected to the first AC input terminal; a third protection diode (Dprot3), where the anode is connected to a second AC input terminal and the cathode is connected to the positive boost output terminal (Obp); and a fourth protection diode (Dprot4), where the anode is connected to the negative boost output terminal (Obn) and the cathode is connected to the second AC input terminal.

Abstract: A Clos-network packet switching system may include input modules coupled to a virtual output queue, central modules coupled to the input modules, and output modules coupled to the central modules, each output module having a plurality of cross-point buffers for storing a packet and one or more output ports for outputting the packet.

Abstract: A method of scheduling tasks for active network measurement includes identifying a first measurement task for measuring a first network parameter and a second measurement task for measuring a second network parameter. It is determined whether there is a conflict between the first measurement task and the second measurement task. A first execution time of the first measurement task and a second execution time of the second measurement task are also determined. A task schedule is generated based at least in part on the first execution time, the second execution time, and whether there is the conflict between the first measurement task and the second measurement task. The task schedule is further generated based at least in part on a color graph.

Abstract: Multicast traffic is expected to increase in packet networks, and therefore in switches and routers, by including broadcast and multimedia-on-demand services. Combined input-crosspoint buffered (CICB) switches can provide high performance under uniform multicast traffic. However this is often at the expense of N2 crosspoint buffers. An output-based shared-memory crosspoint-buffered (O-SMCB) packet switch is used where the crosspoint buffers are shared by two outputs and use no speedup. An embodiment of the proposed switch provides high performance under admissible uniform and non-uniform multicast traffic models while using 50% of the memory used in CICB switches that has dedicated buffers. Furthermore, the O-SMCB switch provides higher throughput than an existing SMCB switch where the buffers are shared by inputs.

Abstract: A configuration scheme for IQC switches that hierarchizes the matching process reduces configuration complexity by performing routing first and port matching afterwards in a three-stage Clos-network switch. This scheme applies the reduction concept of Clos networks to the matching process. This, in turn, results in a feasible size of schedulers for up to Exabit-capacity switches, an independent configuration of the middle stage modules from port matches, a reduction of the matching communication overhead between different stages, and a release of the switching function to the last-stage modules in a three-stage switch. The switching performance of the proposed approach using weight-based and weightless selection schemes is high under uniform and non-uniform traffic. The number of stages of a Clos-network switch can be reduced to two.

Abstract: A pipeline-based matching scheduling approach for input-buffered switches relaxes the timing constraint for arbitration with matching schemes, such as CRRD and CMSD. In the new approach, arbitration may operate in a pipelined manner. Each sub-scheduler is allowed to take more than one time slot for its matching. Every time slot, one of them provides a matching result(s). The sub-scheduler can use a matching scheme such as CRRD and CMSD.

Abstract: A Pipelined-based Maximal-sized Matching (PMM) scheduling approach for input-buffered switches relaxes the timing constraint for arbitration with a maximal matching scheme. In the PMM approach, arbitration may operate in a pipelined manner. Each subscheduler is allowed to take more than one time slot for its matching. Every time slot, one of them provides the matching result. The subscheduler can adopt a pre-existing efficient maximal matching algorithm such as iSLIP and DRRM. PMM maximizes the efficiency of the adopted arbitration scheme by allowing sufficient time for a number of iterations. PMM preserves 100% throughput under uniform traffic and fairness for best-effort traffic.

Abstract: A pipeline-based matching scheduling approach for input-buffered switches relaxes the timing constraint for arbitration with matching schemes, such as CRRD and CMSD. In the new approach, arbitration may operate in a pipelined manner. Each sub-scheduler is allowed to take more than one time slot for its matching. Every time slot, one of them provides a matching result(s). The sub-scheduler can use a matching scheme such as CRRD and CMSD.

Abstract: A synchronized control method for a three-phase three-level boost-type rectifier with reduced input current ripple and balanced output voltages is disclosed. The proposed control allows simplifying the control circuit as much as possible without compromising the rectifier performance. In fact, besides simplicity, the control method featured synchronized command signals to de switching devices, minimized input current ripple, full controllability of the output voltage, dynamic balance of the output center point, constant switching frequency, simplified design of EMC filters, good transient and steady state performance, and low cost. The invention described first the most important configurations that the three-phase three-level boost-type rectifier may assume and studied the converter's operation. The concept involved for output voltage, input current, neutral point balance and control system design was presented.

Abstract: A synchronized control method for a three-phase three-level boost-type rectifier with reduced input current ripple and balanced output voltages is disclosed. The proposed control allows simplifying the control circuit as much as possible without compromising the rectifier performance. In fact, besides simplicity, the control method featured synchronized command signals to de switching devices, minimized input current ripple, full controllability of the output voltage, dynamic balance of the output center point, constant switching frequency, simplified design of EMC filters, good transient and steady state performance, and low cost. The invention described first the most important configurations that the three-phase three-level boost-type rectifier may assume and studied the converter's operation. The concept involved for output voltage, input current, neutral point balance and control system design was presented.

Abstract: A pipeline-based matching scheduling approach for input-buffered switches relaxes the timing constraint for arbitration with matching schemes, such as CRRD and CMSD. In the new approach, arbitration may operate in a pipelined manner. Each sub-scheduler is allowed to take more than one time slot for its matching. Every time slot, one of them provides a matching result(s). The sub-scheduler can use a matching scheme such as CRRD and CMSD.

Abstract: A Pipelined-based Maximal-sized Matching (PMM) scheduling approach for input-buffered switches relaxes the timing constraint for arbitration with a maximal matching scheme. In the PMM approach, arbitration may operate in a pipelined manner. Each subscheduler is allowed to take more than one time slot for its matching. Every time slot, one of them provides the matching result. The subscheduler can adopt a pre-existing efficient maximal matching algorithm such as iSLIP and DRRM. PMM maximizes the efficiency of the adopted arbitration scheme by allowing sufficient time for a number of iterations. PMM preserves 100% throughput under uniform traffic and fairness for best-effort traffic.

Abstract: A pipeline-based matching scheduling approach for input-buffered switches relaxes the timing constraint for arbitration with matching schemes, such as CRRD and CMSD. In the new approach, arbitration may operate in a pipelined manner. Each sub-scheduler is allowed to take more than one time slot for its matching. Every time slot, one of them provides a matching result(s). The sub-scheduler can use a matching scheme such as CRRD and CMSD.

Abstract: A pipeline-based matching scheduling approach for input-buffered switches relaxes the timing constraint for arbitration with matching schemes, such as CRRD and CMSD. In the new approach, arbitration may operate in a pipelined manner. Each sub-scheduler is allowed to take more than one time slot for its matching. Every time slot, one of them provides a matching result(s). The sub-scheduler can use a matching scheme such as CRRD and CMSD.