Abstract: Power is conserved by dynamically applying clocks to execution units in a pipeline of a microprocessor. A clock to an execution unit is applied only when an instruction to the execution unit is valid. At other times when the execution unit needs not to be operational, the clock is not applied to the execution unit. In a preferred embodiment of the invention, a dynamic clock-control unit is used to provide a control signal to a local clock buffer providing a local clock to an execution unit.

Abstract: This invention is a method and system for hybride prediction of load addresses and/or values. The new scheme for value prediction allows to predict last values, strides as well as values out of context without the use of a sophisticated switching scheme between several predictors. The system collects patterns of deltas of subsequent values instead of the values itself in a first table (40). Thus, a last value prediction can be achieved by predicting a ‘pattern’ of just one stride which is zero. A stride predictor uses a pattern of one constant stride. And a certain pattern of values is modelled by recording the pattern of deltas between the values and adding the deltas to the last value. The switching scheme inherently includes the system itself and operates basically by immediate evaluation of counters in the pattern history table (44).

Abstract: An apparatus and a method for performing subroutine call and return operations in a computer having a processor with an instruction prefetch mechanism which includes a branch history table for storing target addresses of a plurality of branch instructions found in an instruction stream. The branch history table 22 contains a potential call instruction tag 37 and a return instruction tag 39. For each potential subroutine call instruction found in a prefetch instruction stream an address pair containing the call target address and the next sequential instruction address of the instruction is stored in a return identification stack 24. Subsequently detected branch instructions initiate an associative search on the next sequential instruction part in the return identification stack where a matching entry identifies the branch instruction as a return instruction. The address pair contained in the matching entry is then transferred to a return cache 30 which is arranged in parallel to the branch history table.

Abstract: A method for addressing internal instructions in an out-of-order processor is proposed, which allows for an efficient register renaming even in case internal instructions are issued to a multitude of window buffers. In this case, it is not clear how internal instructions that stem from one external instruction can be indicated as being "related". In the method proposed, a common instruction identifier is assigned to each of the internal instructions of a group of internal instructions representing an external instruction. Furtheron, an offset identifier is assigned to each of said internal instructions in order to be able to unambiguously identify each of said internal instructions. These two identifiers are used as a tag, in order to be able to resolve data dependencies. By use of the invention, exception handling, recovery of mispredicted branches, and committing related instructions corresponding to one external instruction is simplified.

Abstract: The invention provides an apparatus and a method for converting instructions of a code A to instructions of a code B. Said conversion is performed by obtaining rearrangement information, which corresponds to the instruction that is to be converted, from a table. Said rearrangement information is then used to rearrange the instruction elements of the initial instruction, in order to generate instructions of code B, which functionally corresponds to said initial instruction. Said rearrangement can be performed by multiplexing means, which use said instruction elements of the initial code A instruction as input, and which select one of said instruction elements, or the content of another register, and forward this selected data to the instruction that is to be generated. Said rearrangement information is directly used to control the selection performed by said multiplexers.

Abstract: A method and system for the design verification of logic units capable of providing verification of a logic unit design prior to chip production. At least one test unit is coupled to a logic unit via an interface. The test unit includes a set of operations which are applied to the logic unit. The selection of test operations to be applied to the logic unit and the determination of the start times thereof are executed randomly and independently of each other. Thus, with the present method and system two parameters of the test operation generating event: the sequence of the test operations, and the temporal relationship between the test operations, are independently and randomly modified.

Abstract: A system buffers first and second data buses having asynchronous, different frequency clocks. The system comprises a data buffer interposed between the first and second data buses to receive data from the first bus and supply data to the second bus. The also comprises a write address generator, coupled to the first bus to receive a data available signal and coupled to the data buffer, for generating an address in the data buffer to store the data received from the first bus. The data available signal increments the write address generator. A load record register is coupled to receive an indication that data is being written from the first data bus into the data buffer, and tracks locations in the data buffer which have received data from the first data bus. A read address generator is coupled to the data buffer, and generates an address of the next data, if any, that is stored in the data buffer to be read onto the second data bus.