Patents by Inventor Roman Roth
Roman Roth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11981651Abstract: In a method for aromatizing an alicyclic region of a cannabinoid, especially in enantiopure, scalemic and/or racemic form, in particular for aromatizing the cyclohexene group in ?9-THC-C5, ?9-THCA-C5 A, ?9-THCV-C3, ?9-THCVA-C5 A, and/or scalemic or racemic mixtures of these substances, wherein an oxidizing agent is added to the cannabinoid, sulfur is used as the oxidizing agent.Type: GrantFiled: June 14, 2022Date of Patent: May 14, 2024Assignees: SWISS CANNAPHARMACEUTICAL SA, ETH ZURICHInventors: Erick M. Carreira, Roman Sarott, Patrick Pfaff, Konrad Hurni, Remo Roth, Sarah Eichenberger, Jürg Stäubli
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Publication number: 20230317542Abstract: A semiconductor device is proposed. The semiconductor device includes a contact pad structure over a first surface of a semiconductor body. The semiconductor device further includes a dielectric structure lining a sidewall and a boundary area on a top surface of the contact pad structure, wherein the dielectric structure includes a dielectric spacer at the sidewall of the contact pad structure.Type: ApplicationFiled: March 30, 2023Publication date: October 5, 2023Inventors: Jochen HILSENBECK, Thomas SÖLLRADL, Roman ROTH, Richard GAISBERGER, Sophia OLES, Helmut Heinrich SCHOENHERR, Juergen STEINBRENNER
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Publication number: 20230082571Abstract: A power semiconductor device includes a semiconductor body and a first terminal at the semiconductor body. The first terminal has a first side for adjoining an encapsulation and a second side for adjoining the semiconductor body. The first terminal includes, at the first side, a top layer; and, at the second side, a base layer coupled with the top layer, wherein a sidewall of the top layer and/or a sidewall of the base layer is arranged in an angle smaller than 85° with respect to a plane.Type: ApplicationFiled: September 15, 2022Publication date: March 16, 2023Inventors: Jochen HILSENBECK, Thomas SOELLRADL, Roman ROTH, Annette SAENGER, Ulrike FASTNER, Johanna SCHLAMINGER, Joachim HIRSCHLER, Andreas BEHRENDT
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Patent number: 11315892Abstract: A power semiconductor device, a power semiconductor module and a power semiconductor device processing method are provided. The power semiconductor device includes a first load terminal structure, a second load terminal structure, and a semiconductor structure electrically coupled to each load terminal structure and configured to carry a load current. The first load terminal structure includes a conductive layer in contact with the semiconductor structure, a bonding block configured to be contacted by at least one bond wire and to receive at least a part of the load current from the at least one bond wire and/or the conductive layer, a support block having a hardness greater than the hardness of the conductive layer and the bonding block. The bonding block is mounted on the conductive layer via the support block, and a zone is arranged within the conductive layer and/or the bonding block, the zone exhibiting nitrogen atoms.Type: GrantFiled: August 9, 2018Date of Patent: April 26, 2022Inventors: Roman Roth, Frank Hille, Hans-Joachim Schulze
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Patent number: 10777506Abstract: According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a silicon carbide semiconductor body and a metal adhesion and barrier structure between the metal structure and the silicon carbide semiconductor body. The metal adhesion and barrier structure includes a layer comprising titanium and tungsten.Type: GrantFiled: September 20, 2019Date of Patent: September 15, 2020Assignee: Infineon Technologies AGInventors: Frank Hille, Ravi Keshav Joshi, Michael Fugger, Oliver Humbel, Thomas Laska, Matthias Müller, Roman Roth, Carsten Schaeffer, Hans-Joachim Schulze, Holger Schulze, Juergen Steinbrenner, Frank Umbach
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Patent number: 10756035Abstract: A semiconductor device is presented. The semiconductor device comprises a semiconductor body coupled to a first load terminal and to a second load terminal and configured to carry a load current between the first load terminal and the second load terminal. The first load terminal comprises a contiguous metal layer coupled to the semiconductor body; and at least one metal island arranged on top of and in contact with the contiguous metal layer and configured to be contacted by an end of a bond wire and to receive at least a part of the load current by means of the bond wire, wherein the contiguous metal layer and the metal island are composed of the same metal.Type: GrantFiled: October 4, 2016Date of Patent: August 25, 2020Assignee: Infineon Technologies AGInventors: Roman Roth, Wolfgang Wagner
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Publication number: 20200013722Abstract: According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a silicon carbide semiconductor body and a metal adhesion and barrier structure between the metal structure and the silicon carbide semiconductor body. The metal adhesion and barrier structure includes a layer comprising titanium and tungsten.Type: ApplicationFiled: September 20, 2019Publication date: January 9, 2020Inventors: Frank Hille, Ravi Keshav Joshi, Michael Fugger, Oliver Humbel, Thomas Laska, Matthias Müller, Roman Roth, Carsten Schaeffer, Hans-Joachim Schulze, Holger Schulze, Juergen Steinbrenner, Frank Umbach
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Patent number: 10475743Abstract: According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a semiconductor body and a metal adhesion and barrier structure between the metal structure and the semiconductor body. The metal adhesion and barrier structure includes a first layer having titanium and tungsten, and a second layer having titanium, tungsten, and nitrogen on the first layer having titanium and tungsten.Type: GrantFiled: March 14, 2017Date of Patent: November 12, 2019Assignee: Infineon Technologies AGInventors: Frank Hille, Ravi Keshav Joshi, Michael Fugger, Oliver Humbel, Thomas Laska, Matthias Mueller, Roman Roth, Carsten Schaeffer, Hans-Joachim Schulze, Holger Schulze, Juergen Steinbrenner, Frank Umbach
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Patent number: 10224237Abstract: A method for forming a semiconductor device includes forming an insulating material layer above a semiconductor substrate and modifying at least a portion of a surface of the insulating material layer after forming the insulating material layer. Further, the method includes forming an electrical conductive structure on at least the portion of the surface of the insulating material layer after modifying at least the portion of the surface of the insulating material layer.Type: GrantFiled: May 23, 2017Date of Patent: March 5, 2019Assignee: Infineon Technologies AGInventors: Roman Roth, Frank Umbach
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Publication number: 20180366428Abstract: A power semiconductor device, a power semiconductor module and a power semiconductor device processing method are provided. The power semiconductor device includes a first load terminal structure, a second load terminal structure, and a semiconductor structure electrically coupled to each load terminal structure and configured to carry a load current. The first load terminal structure includes a conductive layer in contact with the semiconductor structure, a bonding block configured to be contacted by at least one bond wire and to receive at least a part of the load current from the at least one bond wire and/or the conductive layer, a support block having a hardness greater than the hardness of the conductive layer and the bonding block. The bonding block is mounted on the conductive layer via the support block, and a zone is arranged within the conductive layer and/or the bonding block, the zone exhibiting nitrogen atoms.Type: ApplicationFiled: August 9, 2018Publication date: December 20, 2018Applicant: Infineon Technologies AGInventors: Roman ROTH, Frank HILLE, Hans-Joachim SCHULZE
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Patent number: 10079217Abstract: A power semiconductor device, a power semiconductor module and a power semiconductor device processing method are provided. The power semiconductor device includes a first load terminal structure, a second load terminal structure, and a semiconductor structure electrically coupled to each load terminal structure and configured to carry a load current. The first load terminal structure includes a conductive layer in contact with the semiconductor structure, a bonding block configured to be contacted by at least one bond wire and to receive at least a part of the load current from the at least one bond wire and/or the conductive layer, a support block having a hardness greater than the hardness of the conductive layer and the bonding block. The bonding block is mounted on the conductive layer via the support block, and a zone is arranged within the conductive layer and/or the bonding block, the zone exhibiting nitrogen atoms.Type: GrantFiled: January 31, 2017Date of Patent: September 18, 2018Assignee: Infineon Technologies AGInventors: Roman Roth, Frank Hille, Hans-Joachim Schulze
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Patent number: 9859272Abstract: A semiconductor device comprising a source region being electrically connected to a first load terminal (E) of the semiconductor device and a drift region comprising a first semiconductor material (M1) having a first band gap, the drift region having dopants of a first conductivity type and being configured to carry at least a part of a load current between the first load terminal (E) and a second load terminal (C) of the semiconductor device, is presented. The semiconductor device further comprises a semiconductor body region having dopants of a second conductivity type complementary to the first conductivity type and being electrically connected to the first load terminal (E), a transition between the semiconductor body region and the drift region forming a pn-junction, wherein the pn-junction is configured to block a voltage applied between the first load terminal (E) and the second load terminal (C).Type: GrantFiled: July 14, 2016Date of Patent: January 2, 2018Assignee: Infineon Technologies AGInventors: Hans-Joachim Schulze, Holger Huesken, Franz-Josef Niedernostheide, Frank Dieter Pfirsch, Roman Roth, Christian Philipp Sandow, Carsten Schaeffer, Stephan Voss
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Publication number: 20170345711Abstract: A method for forming a semiconductor device includes forming an insulating material layer above a semiconductor substrate and modifying at least a portion of a surface of the insulating material layer after forming the insulating material layer. Further, the method includes forming an electrical conductive structure on at least the portion of the surface of the insulating material layer after modifying at least the portion of the surface of the insulating material layer.Type: ApplicationFiled: May 23, 2017Publication date: November 30, 2017Inventors: Roman Roth, Frank Umbach
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Patent number: 9773736Abstract: A method of forming a metallization layer over a semiconductor substrate includes depositing a blanket layer of a diffusion barrier liner over an inter level dielectric layer, and depositing a blanket layer of an intermediate layer over the diffusion barrier liner. A blanket layer of a power metal layer including copper is deposited over the intermediate layer. The intermediate layer includes a solid solution of a majority element and copper. The intermediate layer has a different etch selectivity from the power metal layer. After depositing the power metal layer, structuring the power metal layer, the intermediate layer, and the diffusion barrier liner.Type: GrantFiled: January 28, 2015Date of Patent: September 26, 2017Assignee: Infineon Technologies AGInventors: Ravi Keshav Joshi, Juergen Steinbrenner, Christian Fachmann, Petra Fischer, Roman Roth
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Publication number: 20170271268Abstract: According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a semiconductor body and a metal adhesion and barrier structure between the metal structure and the semiconductor body. The metal adhesion and barrier structure includes a first layer having titanium and tungsten, and a second layer having titanium, tungsten, and nitrogen on the first layer having titanium and tungsten.Type: ApplicationFiled: March 14, 2017Publication date: September 21, 2017Inventors: Frank Hille, Ravi Keshav Joshi, Michael Fugger, Oliver Humbel, Thomas Laska, Matthias Mueller, Roman Roth, Carsten Schaeffer, Hans-Joachim Schulze, Holger Schulze, Juergen Steinbrenner, Frank Umbach
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Publication number: 20170221842Abstract: A power semiconductor device, a power semiconductor module and a power semiconductor device processing method are provided. The power semiconductor device includes a first load terminal structure, a second load terminal structure, and a semiconductor structure electrically coupled to each load terminal structure and configured to carry a load current. The first load terminal structure includes a conductive layer in contact with the semiconductor structure, a bonding block configured to be contacted by at least one bond wire and to receive at least a part of the load current from the at least one bond wire and/or the conductive layer, a support block having a hardness greater than the hardness of the conductive layer and the bonding block. The bonding block is mounted on the conductive layer via the support block, and a zone is arranged within the conductive layer and/or the bonding block, the zone exhibiting nitrogen atoms.Type: ApplicationFiled: January 31, 2017Publication date: August 3, 2017Applicant: Infineon Technologies AGInventors: Roman ROTH, Frank HILLE, Hans-Joachim SCHULZE
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Publication number: 20170098620Abstract: A semiconductor device is presented. The semiconductor device comprises a semiconductor body coupled to a first load terminal and to a second load terminal and configured to carry a load current between the first load terminal and the second load terminal. The first load terminal comprises a contiguous metal layer coupled to the semiconductor body; and at least one metal island arranged on top of and in contact with the contiguous metal layer and configured to be contacted by an end of a bond wire and to receive at least a part of the load current by means of the bond wire, wherein the contiguous metal layer and the metal island are composed of the same metal.Type: ApplicationFiled: October 4, 2016Publication date: April 6, 2017Inventors: Roman Roth, Wolfgang Wagner
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Publication number: 20170025408Abstract: A semiconductor device comprising a source region being electrically connected to a first load terminal (E) of the semiconductor device and a drift region comprising a first semiconductor material (M1) having a first band gap, the drift region having dopants of a first conductivity type and being configured to carry at least a part of a load current between the first load terminal (E) and a second load terminal (C) of the semiconductor device, is presented. The semiconductor device further comprises a semiconductor body region having dopants of a second conductivity type complementary to the first conductivity type and being electrically connected to the first load terminal (E), a transition between the semiconductor body region and the drift region forming a pn-junction, wherein the pn-junction is configured to block a voltage applied between the first load terminal (E) and the second load terminal (C).Type: ApplicationFiled: July 14, 2016Publication date: January 26, 2017Inventors: Hans-Joachim Schulze, Holger Huesken, Franz-Josef Niedernostheide, Frank Dieter Pfirsch, Roman Roth, Christian Philipp Sandow, Carsten Schaeffer, Stephan Voss
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Publication number: 20160218033Abstract: A method of forming a metallization layer over a semiconductor substrate includes depositing a blanket layer of a diffusion barrier liner over an inter level dielectric layer, and depositing a blanket layer of an intermediate layer over the diffusion barrier liner. A blanket layer of a power metal layer including copper is deposited over the intermediate layer. The intermediate layer includes a solid solution of a majority element and copper. The intermediate layer has a different etch selectivity from the power metal layer. After depositing the power metal layer, structuring the power metal layer, the intermediate layer, and the diffusion barrier liner.Type: ApplicationFiled: January 28, 2015Publication date: July 28, 2016Inventors: Ravi Keshav Joshi, Juergen Steinbrenner, Christian Fachmann, Petra Fischer, Roman Roth
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Patent number: 9397022Abstract: A semiconductor device includes a semiconductor substrate having a first side, at least a first area formed in the semiconductor substrate, at least a second area formed in the semiconductor substrate, a first metal layer structure having at least a first metal portion in the first area and at least a second metal portion in the second area, and a second metal layer structure on and in ohmic contact with the first metal portion in the first area while leaving the second metal portion of the first metal layer structure in the second area uncovered. The second metal layer structure and the first metal portion of the first metal layer structure form together a common metallization structure on the first side of the semiconductor substrate in the first area.Type: GrantFiled: October 12, 2015Date of Patent: July 19, 2016Assignee: Infineon Technologies Austria AGInventors: Roman Roth, Frank Umbach