Patents by Inventor Rotem Sela

Rotem Sela has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11954367
    Abstract: Disclosed are systems and methods providing active time-based prioritization in host-managed stream devices. The method includes receiving a plurality of host commands from a host system. The method also includes computing active times of open memory regions. The method also includes determining one or more regions that have remained open for more than a threshold time period, based on the active times. The method also includes prioritizing one or more host commands from amongst the plurality of host commands for completion, the one or more host commands having corresponding logical addresses belonging to the one or more regions, thereby (i) minimizing risk to data and (ii) releasing resources corresponding to the one or more regions.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: April 9, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ramanathan Muthiah, Judah Gamliel Hahn, Rotem Sela
  • Publication number: 20240004559
    Abstract: A mobile data storage device (DSD) incorporating a mobile data storage device (DSD), the mobile DSD comprising a non-volatile storage medium configured to store user data, a data path configured to transmit at least data between the mobile DSD and a host computer system, a housing having a machine readable optical code and a controller. The controller is configured to receive, from the data path, a request to restore the mobile DSD to factory settings. The controller also receives, from the data path, a unique access passcode derived from the machine readable optical code. The controller validates the unique access passcode, and, in response to determining that the unique access passcode is valid, restores the mobile DSD to factory settings.
    Type: Application
    Filed: June 29, 2022
    Publication date: January 4, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Alexander LEMBERG, Rotem SELA, Noam EVEN-CHEN, Asher DRUCK
  • Publication number: 20230409236
    Abstract: Disclosed are systems and methods providing active time-based prioritization in host-managed stream devices. The method includes receiving a plurality of host commands from a host system. The method also includes computing active times of open memory regions. The method also includes determining one or more regions that have remained open for more than a threshold time period, based on the active times. The method also includes prioritizing one or more host commands from amongst the plurality of host commands for completion, the one or more host commands having corresponding logical addresses belonging to the one or more regions, thereby (i) minimizing risk to data and (ii) releasing resources corresponding to the one or more regions.
    Type: Application
    Filed: June 15, 2022
    Publication date: December 21, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ramanathan MUTHIAH, Judah Gamliel HAHN, Rotem SELA
  • Patent number: 11836374
    Abstract: A storage system uses blocks of memory that are sized larger than a size of a zone. This means that the storage system stores multiple zones in a given block. Storing zones with different zone properties in a given block can be problematic, so the storage system obtains zone property information for each zone and stores zones with similar zone properties in a given block.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: December 5, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Einav Zilberstein, Asher Druck
  • Publication number: 20230384966
    Abstract: A storage system uses blocks of memory that are sized larger than a size of a zone. This means that the storage system stores multiple zones in a given block. Storing zones with different one properties in a given block can be problematic, so the storage system obtains zone property information for each zone and stores zones with similar zone properties in a given block.
    Type: Application
    Filed: July 8, 2022
    Publication date: November 30, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Einav Zilberstein, Asher Druck
  • Publication number: 20230367485
    Abstract: The present disclosure generally relates to recognizing a violation of an expected write amplification (WAF) rate and informing a host device of the violation so that the host device may take corrective action and ensure the data storage device does not reach end of life (EOL) earlier than expected. The host can provide the data storage device with an expected lifetime and may additionally provide a benchmark WAF rate. The data storage device compares the actual WAF rate to the benchmark WAF rate and notifies the host device of any violation where the actual WAF rate exceeds the benchmark WAF rate.
    Type: Application
    Filed: May 12, 2022
    Publication date: November 16, 2023
    Inventors: Alexander LEMBERG, Aki BLEYER, Rotem SELA
  • Patent number: 11809747
    Abstract: A storage system analyzes a logical block address range of data in a resolution of a defragmentation unit. The storage system determines whether a given defragmentation unit is fragmented above a threshold and performs a defragmentation operation accordingly. Additionally or alternatively, the storage system can receive a suggested logical block address read order from a host to improve performance.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: November 7, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Einav Zilberstein, Hadas Oshinsky, Oren Ben Hayun, Rotem Sela, Alex Lemberg
  • Patent number: 11782648
    Abstract: A storage system and method for host memory access are provided. In one embodiment, a storage system is configured to receive a write command from a host that is recognized by the storage system as a read host memory command and receive a read command from the host that is recognized by the storage system as a write host memory command. This provides a communication channel that allows the storage system to access the host memory. The storage system can use the host memory as a backup write cache and/or to stream data of different types stored in different areas of the host memory. Hibernation can be avoided, and timeout delays can be ignored. Other embodiments are provided.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: October 10, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Amir Shaharabany, Eliad Adi Klein
  • Publication number: 20230305756
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to maintain a plurality of virtual pools, wherein each virtual pool corresponds with an logical block address (LBA) range, update a counter of a virtual pool, wherein the counter corresponds to a health of the LBA range, and select, based on the counter, the virtual pool to program data to. The controller is further configured to maintain a counter for each application having data programmed to the virtual pool, where the counter is increased for each write operation to the virtual pool. When the counter equals or exceeds a threshold value, the controller is configured to send a warning to each application associated with the virtual pool having the counter that equals or exceeds the threshold value.
    Type: Application
    Filed: March 20, 2023
    Publication date: September 28, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Rotem SELA, Asher DRUCK
  • Publication number: 20230195376
    Abstract: A storage system analyzes a logical block address range of data in a resolution of a defragmentation unit. The storage system determines whether a given defragmentation unit is fragmented above a threshold and performs a defragmentation operation accordingly. Additionally or alternatively, the storage system can receive a suggested logical block address read order from a host to improve performance.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 22, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Einav Zilberstein, Hadas Oshinsky, Oren Ben Hayun, Rotem Sela, Alex Lemberg
  • Patent number: 11675512
    Abstract: A storage system allocates single-level cell (SLC) blocks in its memory to act as a write buffer and/or a read buffer. When the storage system uses the SLC blocks as a read buffer, the storage system reads data from multi-level cell (MLC) blocks in the memory and stores the data in the read buffer prior to receiving a read command from a host for the data. When the storage system uses the SLC blocks as a write buffer, the storage system retains certain data in the write buffer while other data is flushed from the write buffer to MLC blocks in the memory.
    Type: Grant
    Filed: August 1, 2022
    Date of Patent: June 13, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Einav Zilberstein, Karin Inbar
  • Publication number: 20230035584
    Abstract: The present disclosure generally relates to utilizing the host clock signal frequency to determine whether to operate in the default pulse width modulation (PWM) link startup sequence (LSS), be changed to high speed (HS) LSS by a host device capable of operating in either PWM LSS or HS LSS, or ignore the data storage device attributes of operating in PWM LSS and instead operate according to HS LSS. In so doing, the data storage device is adaptable to work with older generation UFS host devices as well as current and future generation UFS host devices.
    Type: Application
    Filed: July 27, 2022
    Publication date: February 2, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Shemmer Choresh
  • Patent number: 11537320
    Abstract: A storage system and method for host memory access are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive a write command from the host that is recognized by the storage system as a read host memory command; in response to receiving the write command, send an identification of a location in the host memory to the host; and receive, from the host, data that is stored in the location in the host memory. Other embodiments are provided.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: December 27, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Amir Shaharabany, Eliad Adi Klein
  • Publication number: 20220365679
    Abstract: A storage system allocates single-level cell (SLC) blocks in its memory to act as a write buffer and/or a read buffer. When the storage system uses the SLC blocks as a read buffer, the storage system reads data from multi-level cell (MLC) blocks in the memory and stores the data in the read buffer prior to receiving a read command from a host for the data. When the storage system uses the SLC blocks as a write buffer, the storage system retains certain data in the write buffer while other data is flushed from the write buffer to MLC blocks in the memory.
    Type: Application
    Filed: August 1, 2022
    Publication date: November 17, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Einav Zilberstein, Karin Inbar
  • Patent number: 11435920
    Abstract: A storage system allocates single-level cell (SLC) blocks in its memory to act as a write buffer and/or a read buffer. When the storage system uses the SLC blocks as a read buffer, the storage system reads data from multi-level cell (MLC) blocks in the memory and stores the data in the read buffer prior to receiving a read command from a host for the data. When the storage system uses the SLC blocks as a write buffer, the storage system retains certain data in the write buffer while other data is flushed from the write buffer to MLC blocks in the memory.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: September 6, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Einav Zilberstein, Karin Inbar
  • Publication number: 20220236919
    Abstract: A storage system and method for host memory access are provided. In one embodiment, a storage system is configured to receive a write command from a host that is recognized by the storage system as a read host memory command and receive a read command from the host that is recognized by the storage system as a write host memory command. This provides a communication channel that allows the storage system to access the host memory. The storage system can use the host memory as a backup write cache and/or to stream data of different types stored in different areas of the host memory. Hibernation can be avoided, and timeout delays can be ignored. Other embodiments are provided.
    Type: Application
    Filed: April 11, 2022
    Publication date: July 28, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Amir Shaharabany, Eliad Adi Klein
  • Publication number: 20220229555
    Abstract: A storage system allocates single-level cell (SLC) blocks in its memory to act as a write buffer and/or a read buffer. When the storage system uses the SLC blocks as a read buffer, the storage system reads data from multi-level cell (MLC) blocks in the memory and stores the data in the read buffer prior to receiving a read command from a host for the data. When the storage system uses the SLC blocks as a write buffer, the storage system retains certain data in the write buffer while other data is flushed from the write buffer to MLC blocks in the memory.
    Type: Application
    Filed: February 24, 2021
    Publication date: July 21, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Einav Zilberstein, Karin Inbar
  • Patent number: 11327684
    Abstract: A storage system and method for host memory access are provided. In one embodiment, a storage system is configured to receive a write command from a host that is recognized by the storage system as a read host memory command and receive a read command from the host that is recognized by the storage system as a write host memory command. This provides a communication channel that allows the storage system to access the host memory. The storage system can use the host memory as a backup write cache and/or to stream data of different types stored in different areas of the host memory. Hibernation can be avoided, and timeout delays can be ignored. Other embodiments are provided.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: May 10, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Amir Shaharabany, Eliad Adi Klein
  • Publication number: 20210357148
    Abstract: A storage system and method for host memory access are provided. In one embodiment, a storage system is configured to receive a write command from a host that is recognized by the storage system as a read host memory command and receive a read command from the host that is recognized by the storage system as a write host memory command. This provides a communication channel that allows the storage system to access the host memory. The storage system can use the host memory as a backup write cache and/or to stream data of different types stored in different areas of the host memory. Hibernation can be avoided, and timeout delays can be ignored. Other embodiments are provided.
    Type: Application
    Filed: May 14, 2020
    Publication date: November 18, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Amir Shaharabany, Eliad Adi Klein
  • Patent number: 11169744
    Abstract: Data may be read from a data storage device using host performance booster (HPB). An encoded HPB entry in a read command provides the PBA (Physical Block Address) as well as the run length. The LBA (Logical Block Address), PBA, and run length are placed in an HPB read buffer table. The HPB read buffer table is located in the host device. When the read command is received by the data storage device, the data storage device reads the LBA, transfer length, and HPB entry from the read command. The HPB entry contains the PBA for the LBA as well as the run length for the data to be read. For non-sequential reads, the HPB contains the LBA, transfer length, and reference to a write buffer table that is stored in the data storage device.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: November 9, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: David C. Brief, Rotem Sela, Opher Lieber