Patents by Inventor Ruby B. Lee

Ruby B. Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11991209
    Abstract: A system for security health monitoring and attestation of virtual machines in cloud computing systems is provided. The system includes a cloud server having a virtual machine and a hypervisor. The cloud server collects security measurement information and signs and hashes the security measurement information using a cryptography engine. The system also includes an attestation server for receiving the hashed security measurement information from the cloud server. The attestation server also verifies the signature and hash values, and interprets the security measurement information. The attestation server generates an attestation report based on the verification and interpretation of the security measurement information.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: May 21, 2024
    Assignee: CoreSecure Technologies, LLC
    Inventors: Ruby B. Lee, Tianwei Zhang
  • Patent number: 11481495
    Abstract: A method, apparatus and system for anomaly detection in a processor based system includes training a deep learning sequence prediction model using observed baseline behavioral sequences of at least one processor behavior of the processor based system, predicting baseline behavioral sequences from the observed baseline behavioral sequences using the sequence prediction model, determining a baseline reconstruction error distribution profile using the baseline behavioral sequences and the predicted baseline behavioral sequences, predicting test behavioral sequences from observed, test behavioral sequences using the sequence prediction model, determining a testing reconstruction error distribution profile using the observed test behavioral sequences and the predicted test behavioral sequences, and comparing the baseline reconstruction error distribution profile to the testing reconstruction error distribution profile to determine if an anomaly exists in a processor behavior of the processor based system.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: October 25, 2022
    Assignee: SRI International
    Inventors: Sek M. Chai, Zecheng He, Aswin Nadamuni Raghavan, Ruby B. Lee
  • Publication number: 20210365590
    Abstract: Systems and methods for random fill caching and prefetching for secure cache memories are provided. The system dynamically de-correlates fetching a cache line to the processor from filling the cache with this cache line, due to a demand memory access, in order to provide greater security from information leakage due to cache side-channel attacks on cache memories. The system includes a random fill engine which includes a random number generator and an adjustable random fill window. Also provided is an adaptive random fill caching system which dynamically adapts the random fill window to a wide variety of computational workloads. Systems and methods for cache prefetching to improve system performance using adaptive random fill prefetching and random fill prefetching are also provided.
    Type: Application
    Filed: March 22, 2021
    Publication date: November 25, 2021
    Applicant: CoreSecure Technologies, LLC
    Inventors: Ruby B. Lee, Fangfei Liu
  • Patent number: 10956617
    Abstract: Systems and methods for random fill caching and prefetching for secure cache memories are provided. The system dynamically de-correlates fetching a cache line to the processor from filling the cache with this cache line, due to a demand memory access, in order to provide greater security from information leakage due to cache side-channel attacks on cache memories. The system includes a random fill engine which includes a random number generator and an adjustable random fill window. Also provided is an adaptive random fill caching system which dynamically adapts the random fill window to a wide variety of computational workloads. Systems and methods for cache prefetching to improve system performance using adaptive random fill prefetching and random fill prefetching are also provided.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: March 23, 2021
    Assignee: CoreSecure Technologies, LLC
    Inventors: Ruby B. Lee, Fangfei Liu
  • Publication number: 20210084075
    Abstract: A system for security health monitoring and attestation of virtual machines in cloud computing systems is provided. The system includes a cloud server having a virtual machine and a hypervisor. The cloud server collects security measurement information and signs and hashes the security measurement information using a cryptography engine. The system also includes an attestation server for receiving the hashed security measurement information from the cloud server. The attestation server also verifies the signature and hash values, and interprets the security measurement information. The attestation server generates an attestation report based on the verification and interpretation of the security measurement information.
    Type: Application
    Filed: September 15, 2020
    Publication date: March 18, 2021
    Applicant: CoreSecure Technologies, LLC
    Inventors: Ruby B. Lee, Tianwei Zhang
  • Patent number: 10838758
    Abstract: Disclosed is a system comprising a physical memory, a processor and a software component. The software component includes a policy/domain handler for receiving data and a policy associated with the data; a hypervisor; and a file management module. The file management module receives a request from a third-party application to interact with a data file containing the data; sends an authorization and tag request to the policy/domain handler to check if the user and application are permitted to access the data, and if permitted, to generate hardware tags for the data file; and sends a secure data request to the hypervisor to create a secure data compartment for the data file and the hardware tags. Based on the authorization and tag request, and the security policy associated with the data, the policy/domain handler generates the hardware tags for the data file.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: November 17, 2020
    Assignee: Teleputers, LLC
    Inventors: Ruby B. Lee, Pramod A. Jamkhedkar, Yu-Yuan Chen
  • Publication number: 20200293657
    Abstract: A method, apparatus and system for anomaly detection in a processor based system includes training a deep learning sequence prediction model using observed baseline behavioral sequences of at least one processor behavior of the processor based system, predicting baseline behavioral sequences from the observed baseline behavioral sequences using the sequence prediction model, determining a baseline reconstruction error distribution profile using the baseline behavioral sequences and the predicted baseline behavioral sequences, predicting test behavioral sequences from observed, test behavioral sequences using the sequence prediction model, determining a testing reconstruction error distribution profile using the observed test behavioral sequences and the predicted test behavioral sequences, and comparing the baseline reconstruction error distribution profile to the testing reconstruction error distribution profile to determine if an anomaly exists in a processor behavior of the processor based system.
    Type: Application
    Filed: May 13, 2019
    Publication date: September 17, 2020
    Inventors: Sek M. Chai, Zecheng He, Aswin Nadamuni Raghavan, Ruby B. Lee
  • Patent number: 10778720
    Abstract: A system for security health monitoring and attestation of virtual machines in cloud computing systems is provided. The system includes a cloud server having a virtual machine and a hypervisor. The cloud server collects security measurement information and signs and hashes the security measurement information using a cryptography engine. The system also includes an attestation server for receiving the hashed security measurement information from the cloud server. The attestation server also verifies the signature and hash values, and interprets the security measurement information. The attestation server generates an attestation report based on the verification and interpretation of the security measurement information.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: September 15, 2020
    Assignee: Teleputers, LLC
    Inventors: Ruby B. Lee, Tianwei Zhang
  • Publication number: 20190171476
    Abstract: Disclosed is a system comprising a physical memory, a processor and a software component. The software component includes a policy/domain handler for receiving data and a policy associated with the data; a hypervisor; and a file management module. The file management module receives a request from a third-party application to interact with a data file containing the data; sends an authorization and tag request to the policy/domain handler to check if the user and application are permitted to access the data, and if permitted, to generate hardware tags for the data file; and sends a secure data request to the hypervisor to create a secure data compartment for the data file and the hardware tags. Based on the authorization and tag request, and the security policy associated with the data, the policy/domain handler generates the hardware tags for the data file.
    Type: Application
    Filed: January 22, 2019
    Publication date: June 6, 2019
    Applicant: Teleputers, LLC
    Inventors: Ruby B. Lee, Pramod A. Jamkhedkar, Yu-Yuan Chen
  • Patent number: 10185584
    Abstract: Disclosed is a system comprising a physical memory, a processor and a software component. The software component includes a policy/domain handler for receiving data and a policy associated with the data; a hypervisor; and a file management module. The file management module receives a request from a third-party application to interact with a data file containing the data; sends an authorization and tag request to the policy/domain handler to check if the user and application are permitted to access the data, and if permitted, to generate hardware tags for the data file; and sends a secure data request to the hypervisor to create a secure data compartment for the data file and the hardware tags. Based on the authorization and tag request, and the security policy associated with the data, the policy/domain handler generates the hardware tags for the data file.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: January 22, 2019
    Assignee: Teleputers, LLC
    Inventors: Ruby B. Lee, Pramod A. Jamkhedkar, Yu-Yuan Chen
  • Patent number: 9989043
    Abstract: A system and method for processor-based security is provided, for on-chip security and trusted computing services for software applications. A processor is provided having a processor core, a cache memory, a plurality of registers for storing at least one hash value and at least one encryption key, a memory interface, and at least one on-chip instruction for creating a secure memory area in a memory external to the processor, and a hypervisor program executed by the processor. The hypervisor program instructs the processor to execute the at least one on-chip instruction to create a secure memory area for a software area for a software module, and the processor encrypts data written to, and decrypts data read from, the external memory using the at least one encryption key and the verifying data read from the external memory using the at least one hash value.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: June 5, 2018
    Assignee: Teleputers, LLC
    Inventors: Ruby B. Lee, David Champagne
  • Publication number: 20180045189
    Abstract: A system and method for processor-based security is provided, for on-chip security and trusted computing services for software applications. A processor is provided having a processor core, a cache memory, a plurality of registers for storing at least one hash value and at least one encryption key, a memory interface, and at least one on-chip instruction for creating a secure memory area in a memory external to the processor, and a hypervisor program executed by the processor. The hypervisor program instructs the processor to execute the at least one on-chip instruction to create a secure memory area for a software area for a software module, and the processor encrypts data written to, and decrypts data read from, the external memory using the at least one encryption key and the verifying data read from the external memory using the at least one hash value.
    Type: Application
    Filed: October 10, 2017
    Publication date: February 15, 2018
    Applicant: Teleputers, LLC
    Inventors: Ruby B. Lee, David Champagne
  • Patent number: 9864703
    Abstract: A cache memory having enhanced performance and security feature is provided. The cache memory includes a data array storing a plurality of data elements, a tag array storing a plurality of tags corresponding to the plurality of data elements, and an address decoder which permits dynamic memory-to-cache mapping to provide enhanced security of the data elements, as well as enhanced performance. The address decoder receives a context identifier and a plurality of index bits of an address passed to the cache memory, and determines whether a matching value in a line number register exists. The line number registers allow for dynamic memory-to-cache mapping, and their contents can be modified as desired. Methods for accessing and replacing data in a cache memory are also provided, wherein a plurality of index bits and a plurality of tag bits at the cache memory are received.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: January 9, 2018
    Assignee: Teleputers, LLC
    Inventors: Ruby B. Lee, Zhenghong Wang
  • Patent number: 9784260
    Abstract: A system and method for processor-based security is provided, for on-chip security and trusted computing services for software applications. A processor is provided having a processor core, a cache memory, a plurality of registers for storing at least one hash value and at least one encryption key, a memory interface, and at least one on-chip instruction for creating a secure memory area in a memory external to the processor, and a hypervisor program executed by the processor. The hypervisor program instructs the processor to execute the at least one on-chip instruction to create a secure memory area for a software area for a software module, and the processor encrypts data written to, and decrypts data read from, the external memory using the at least one encryption key and the verifying data read from the external memory using the at least one hash value.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: October 10, 2017
    Assignee: Teleputers, LLC
    Inventors: Ruby B. Lee, David Champagne
  • Publication number: 20170227995
    Abstract: A method and system capable of implicitly authenticating users based on information gathered from one or more sensors, which may be located in one or more devices, and an authentication model trained via a machine learning technique. Data is collected, manipulated, and assessed with the authentication model in order to determine if the user is authentic. A wide variety of sensors may be utilized, including sensors in smartphones, smartwatches, other wearable devices, and other sensors accessible via an internet of things (IoT) system. The method and system can include continuously testing the user's behavior patterns and environment characteristics, and allowing authentication without interrupting the user's other interactions with a given device or requiring explicit user input. The method and system may also involve the authentication model being retrained, or adaptively updated to include temporal changes in the user's patterns.
    Type: Application
    Filed: February 9, 2017
    Publication date: August 10, 2017
    Applicant: The Trustees of Princeton University
    Inventors: Ruby B. Lee, Wei-Han Lee
  • Publication number: 20160366185
    Abstract: A system for security health monitoring and attestation of virtual machines in cloud computing systems is provided. The system includes a cloud server having a virtual machine and a hypervisor. The cloud server collects security measurement information and signs and hashes the security measurement information using a cryptography engine. The system also includes an attestation server for receiving the hashed security measurement information from the cloud server. The attestation server also verifies the signature and hash values, and interprets the security measurement information. The attestation server generates an attestation report based on the verification and interpretation of the security measurement information.
    Type: Application
    Filed: June 10, 2016
    Publication date: December 15, 2016
    Applicant: Teleputers, LLC
    Inventors: Ruby B. Lee, Tianwei Zhang
  • Publication number: 20160246736
    Abstract: A system and method for processor-based security is provided, for on-chip security and trusted computing services for software applications. A processor is provided having a processor core, a cache memory, a plurality of registers for storing at least one hash value and at least one encryption key, a memory interface, and at least one on-chip instruction for creating a secure memory area in a memory external to the processor, and a hypervisor program executed by the processor. The hypervisor program instructs the processor to execute the at least one on-chip instruction to create a secure memory area for a software area for a software module, and the processor encrypts data written to, and decrypts data read from, the external memory using the at least one encryption key and the verifying data read from the external memory using the at least one hash value. Secure module interactions are provided, as well as the generation of a power-on key which can be used to protect memory in the event of a re-boot event.
    Type: Application
    Filed: May 27, 2014
    Publication date: August 25, 2016
    Applicant: TELEPUTERS, LLC
    Inventors: Ruby B. Lee, David Champagne
  • Publication number: 20160170889
    Abstract: Systems and methods for random fill caching and prefetching for secure cache memories are provided. The system dynamically de-correlates fetching a cache line to the processor from filling the cache with this cache line, due to a demand memory access, in order to provide greater security from information leakage due to cache side-channel attacks on cache memories. The system includes a random fill engine which includes a random number generator and an adjustable random fill window. Also provided is an adaptive random fill caching system which dynamically adapts the random fill window to a wide variety of computational workloads. Systems and methods for cache prefetching to improve system performance using adaptive random fill prefetching and random fill prefetching are also provided.
    Type: Application
    Filed: December 14, 2015
    Publication date: June 16, 2016
    Applicant: Teleputers, LLC
    Inventors: Ruby B. Lee, Fangfei Liu
  • Patent number: 9317708
    Abstract: A trust system and method is disclosed for use in computing devices, particularly portable devices, in which a central Authority shares secrets and sensitive data with users of the respective devices. The central Authority maintains control over how and when shared secrets and data are used. In one embodiment, the secrets and data are protected by hardware-rooted encryption and cryptographic hashing, and can be stored securely in untrusted storage. The problem of transient trust and revocation of data is reduced to that of secure key management and keeping a runtime check of the integrity of the secure storage areas containing these keys (and other secrets). These hardware-protected keys and other secrets can further protect the confidentiality and/or integrity of any amount of other information of arbitrary size (e.g., files, programs, data) by the use of strong encryption and/or keyed-hashing, respectively.
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: April 19, 2016
    Assignee: Teleputers, LLC
    Inventors: Ruby B. Lee, Jeffrey S. Dwoskin
  • Publication number: 20150356026
    Abstract: A cache memory having enhanced performance and security feature is provided. The cache memory includes a data array storing a plurality of data elements, a tag array storing a plurality of tags corresponding to the plurality of data elements, and an address decoder which permits dynamic memory-to-cache mapping to provide enhanced security of the data elements, as well as enhanced performance. The address decoder receives a context identifier and a plurality of index bits of an address passed to the cache memory, and determines whether a matching value in a line number register exists. The line number registers allow for dynamic memory-to-cache mapping, and their contents can be modified as desired. Methods for accessing and replacing data in a cache memory are also provided, wherein a plurality of index bits and a plurality of tag bits at the cache memory are received.
    Type: Application
    Filed: August 17, 2015
    Publication date: December 10, 2015
    Applicant: TELEPUTERS, LLC
    Inventors: Ruby B. Lee, Zhenghong Wang