Abstract: The present invention provides permutation instructions which can be used in software executed in a programmable processor for solving permutation problems in cryptography, multimedia and other applications. The permute instructions are based on a Benes network comprising two butterfly networks of the same size connected back-to-back. Intermediate sequences of bits are defined that an initial sequence of bits from a source register are transformed into. Each intermediate sequence of bits is used as input to a subsequent permutation instruction. Permutation instructions are determined for permitting the initial source sequence of bits into one or more intermediate sequence of bits until a desired sequence is obtained. The intermediate sequences of bits are determined by configuration bits. The permutation instructions form a permutation instruction sequence of at least one instruction.

Abstract: Compare-plus-tally instructions are used to enhance video-compression performance by providing for faster computations of block-match measures. The invention is most useful in the context of comparing blocks from reference and predicted frames, where the luminance data for the blocks has been reduced to 1-bit-per-pixel relative to local average luminance. A combined XOR and tally instruction can be used in a two-instruction loop with an accumulate instruction to provide a block-match measure. Alternatively, a single instruction can implement an accumulation along with the comparison and tally to provide a one-instruction loop. Furthermore, the tallying and accumulation can be performed on a subword basis, with a final TreeAdd instruction summing across subwords outside the loop.

Abstract: Parallel table lookups are implemented using variable Mux instructions to reorder data. Table data can be represented in a “table” register, while the desired ordering can be represented in an “Index” register. A direct variable Mux instruction can specify the table register and the index register as arguments, along with a result register. The instruction writes at least some of the data from the table register into the result register as specified in the index register. If the entire table cannot fit within a single register, entries can be divided between two or more table registers. An indirect variable Mux instruction can specify both a table-register-select register and a subword-location-select register. Both the direct and indirect Mux instructions can be used with entry data that is divided in accordance with significance between registers. In that case, plural Mux instructions are used with UnPack instructions that concatenate portions of the table entries.

Abstract: Intra-register subword add instructions yield results that are a function of a sum having as at least some of its addends unary functions of at least two subwords stored in the same register. For example, one “TreeAdd” instruction yields a sum of all subwords in a register. A “parallel accumulate” PAcc instruction yields a result with four 2-byte result subwords. Each result subword is the sum of 2-byte value in a first operand register and two of eight 1-byte subwords in a second operand register. A “Parallel Accumulate Magnitude” PAccMagLR also yields a result with four 2-byte subwords. Each of these subwords is the sum of a 2-byte value in a first operand register and the absolute values of two 1-byte values in a second operand register. These instructions provide for substantial performance enhancements for motion estimation used in video compression.

Abstract: Motion estimation uses tally (Population Count) and XOR (or other bit-wise comparison) operations to obtain a block-match measure for reference and predicted blocks to identify motion vectors for use in video compression. The XOR operations can be performed on absolute or relative luminance data. For example, a one-bit-per-pixel representation of a block can indicate for each pixel its luminance relative to a local average luminance. The performance improvement offered by the invention (relative to methods using the absolute value of the differences of absolute luminance values) can more than offset a penalty in block-match accuracy due to loss of information in luminance data reduction and/or the ignoring of bit significance due to the bit-wise comparison.

Abstract: The present invention provides permutation instructions which can be used in software executed in a programmable processor for solving permutation problems in cryptography, multimedia and other applications. The permute instructions are based on an omega-flip network comprising at least two stages in which each stage can perform the function of either an omega network stage or a flip network stage. Intermediate sequences of bits are defined that an initial sequence of bits from a source register are transformed into. Each intermediate sequence of bits is used as input to a subsequent permutation instruction. Permutation instructions are determined for permuting the initial source sequence of bits into one or more intermediate sequence of bits until a desired sequence is obtained. The intermediate sequences of bits are determined by configuration bits. The permutation instructions form a permutation instruction sequence, of at least one instruction.

Abstract: The present invention provides permutation instructions which can be used in software executed in a programmable processor for solving permutation problems in cryptography, multimedia and other applications. PPERM and PPERM3R instructions are defined to perform permutations by a sequence of instructions with each sequence specifying the position in the source for each bit in the destination. In the PPERM instruction bits in the destination register that change are updated and bits in the destination register that do not change are set to zero. In the PPERM3R instruction bits in the destination register that change are updated and bits in the destination register that do not change are copied from intermediate result of previous PPERM3R instructions. Both PPERM and PPERM3R instruction can individually do permutation with bit repetition. Both PPERM and PPERM3R instruction can individually do permutation of bits stored in more than one register.

Abstract: An apparatus for operating on the contents of an input register to generate the contents of an output register which contains a permutation, with or without repetitions, or a combination of the contents of the input register. The apparatus partitions the input register into a plurality of sub-words, each sub-word being characterized by a location in the input register and a length greater than one bit. In response to an instruction specifying a rearrangement of the input register, the present invention directs at least one of the sub-words in the input register to a location in the output register that differs from the location occupied by the sub-word in the input register. The ordering of the sub-words in the output register differ from the order obtainable by a single shift instruction. In the preferred embodiment of the present invention, the invention is implemented by modifying a conventional shifter comprising a plurality of layers of multiplexers.

Abstract: The present invention provides permutation instructions which can be used in software executed in a programmable processor for solving permutation problems in cryptography, multimedia and other applications. The permute instructions are based on a Benes network comprising two butterfly networks of the same size connected back-to-back. Intermediate sequences of bits are defined that an initial sequence of bits from a source register are transformed into. Each intermediate sequence of bits is used as input to a subsequent permutation instruction. Permutation instructions are determined for permitting the initial source sequence of bits into one or more intermediate sequence of bits until a desired sequence is obtained. The intermediate sequences of bits are determined by configuration bits. The permutation instructions form a permutation instruction sequence of at least one instruction.

Abstract: The method and system provides a set of permutation primitives for current and future 2-D multimedia programs which are based on decomposing images and objects into atomic units, then finding the permutations desired for the atomic units. The subword permutation instructions for these 2-D building blocks are also defined for larger subword sizes at successively higher hierarchical levels. The atomic unit can be a 2×2 matrix and four triangles contained within the 2×2 matrix. Each of the elements in the matrix can represent a subword of one or more bits. The permutations provide vertical, horizontal, diagonal, rotational, and other rearrangements of the elements in the atomic unit.

Abstract: A system allows parallel data processing within a single processor. In order to allow for parallel processing of data, an arithmetic logic unit or other operation executing entity within the processing system such as a shifter is partitioned. Within each partition operations are performed on a portion of one or more operands. When the operation is to be performed on full word length operands, there is no parallel processing. Thus data is allowed to freely propagate across boundaries between the partitions. When performing the operation in parallel using a plurality of operands of less than one full word in length, data is prevented from being propagated across at least one boundary between the partitions. The principles of the present invention may also be utilized to implement a multiplier which performs parallel multiplication of partial word multiplicands.

Abstract: A N-bit by N-bit multiplication apparatus having the ability to select a part of the multiplication result for storage into a result register N-bits wide. A first embodiment of the invention allows a sequence of n-bits from the N-bit by N-bit multiply result to be stored into an N-bit wide register. N+1 to 1 multiplexors are utilized to select which of the multiply result bits are stored into the result register in response to a computer instruction. The second preferred embodiment utilizes multiplexors having fewer than N+1 inputs to select discrete subsets of the multiply result bits for storage into the N-bit wide result register. In this manner, less complex multiplexors are required which take less chip area to implement. The third preferred embodiment utilizes multiple sets of multiplexors to select multiple subresults generated by a parallel multiplication operation. The multiple subresults are stored in a single result register.

Abstract: A computer instruction and apparatus for performing a N-bit by N-bit multiplication and having the ability to select a part of the multiplication result for storage into a result register N-bits wide. A first embodiment of the invention allows a sequence of n-bits from the N-bit by N-bit multiply result to be stored into an N-bit wide register. N+1 to 1 multiplexors are utilized to select which of the multiply result bits are stored into the result register in response to a multiply and select computer instruction. The second preferred embodiment utilizes multiplexors having fewer than N+1 inputs to select discrete subsets of the multiply result bits for storage into the N-bit wide result register. In this manner, less complex multiplexors are required which take less chip area to implement. The third preferred embodiment utilizes multiple sets of multiplexors to select multiple subresults generated by a parallel multiplication operation. The multiple subresults are stored in a single result register.

Abstract: An inverse discrete cosine transform ("IDCT") implementation specifically for the decompression of JPEG, MPEG and Px64 encoded image and video data uses a preprocessing step embedded in a Huffman decoding process to classify data blocks prior to computing the IDCT. The use of data block classification, along with the use of pruned IDCTs appropriate for the specific block class, reduces the total number of multiply and addition operations necessary to decompress an encoded data block, and thereby allows faster data decompression. Synthesis of coefficients suitable for multiplication allows efficient implementation of the novel decompression technique in typical microprocessor architectures, including RISC processor architectures.

Abstract: A computer system provides handling of positive and negative overflow. A first arithmetic operation is performed on a first n-bit unsigned binary operand and a second n-bit signed binary operand to produce an n-bit unsigned binary result. Overflow detection logic circuitry within the arithmetic logic unit detects positive overflow or negative overflow resulting from the arithmetic operation. When there is a positive overflow, saturation logic replaces the output of the two's complement adder with a value of 2.sup.n-1. When there is a negative overflow, the saturation logic replaces the output of the two's complement adder with a value of 0. In an alternate embodiment, a first arithmetic operation is performed on a first n-bit signed binary operand and a second n-bit signed binary operand to produce an n-bit positive signed binary result. For example the arithmetic operation is an addition or subtraction performed by a two's complement adder.

Abstract: A circuit for shifting the bits of an X word to obtain a Y word which is rounded to the nearest odd integer if any bit having the value 1 was shifted off of the word during the shifting operation. The circuit avoids biasing in the integer rounding operation. The shifting operations are accomplished with the aid of multiplexing circuits. The rounding operation is accomplished with the aid of multiplexing circuits that connect the least significant bit of Y to (X.sub.0 OR X.sub.1 OR . . . X.sub.m), where m is the number of places by which X is shifted.

Abstract: An apparatus for combining the contents of an X register, shifted by m places, with the contents of a Y register to generate a result Z. The functional unit can also be configured to perform parallel operations on sub-operands in the X and Y registers. The division of the apparatus into sub-operands is controlled by a mask which specifies the boundary of the sub-operands. The shifting operation is accomplished by multiplexers that connect the p.sup.th bit of the X register to the adder stage that operates on bit Y.sub.p-m of the Y register. Circuitry is provided at the boundary of the sub-operands to prevent the bit signals corresponding to the X register from being routed across a sub-operand boundary. Similarly, circuitry is provided for preventing the carry output of an adder stage that operates on one sub-operand from being propagated to an adder stage that operates on another sub-operand.

Abstract: A method for operating a digital computer in response to the occurrence of an exception is disclosed. The method provides for the examination both of the contents of a predetermined computer location and of the instruction code for the instruction causing the exception. The computer then utilizes the result of those examinations to determine the dismissibility of the exception. The computer transfers control to the next instruction after the instruction which caused the exception if that instruction is dismissible.

Abstract: In a computing system which has memory and an instruction pipeline, a method and apparatus allows for nullification of a second instruction responsive to the state of a nullification field in a first instruction executed prior to the second instruction. After the first instruction is fetched, the operation specified by the first instruction is performed and the results of the operation are stored, including the state of the nullification field. The second instruction is fetched and the operation specified by the second operation is performed. However, conditional upon the state of the nullification field of the first instruction, results, errors, traps and interrupts of the second instruction are not stored in the computer system.

Abstract: An instruction is presented to the cache; the instruction includes a cache control specifier which identifies a type of data being requested. Based on the cache control specifier, one of a plurality of replacement schemes is selected for swapping a data block out of the cache.