Patents by Inventor Ruizhi Shi

Ruizhi Shi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190101697
    Abstract: An integrated optical device fabricated in the back end of line process located within the vertical span of the metal stack and having one or more advantages over a corresponding integrated optical device fabricated in the silicon on insulator layer.
    Type: Application
    Filed: September 18, 2018
    Publication date: April 4, 2019
    Inventors: Ruizhi Shi, Michael J. Hochberg, Ari Jason Novack, Thomas Wetteland Baehr-Jones
  • Publication number: 20190094468
    Abstract: A composite optical waveguide is constructed using an array of waveguide cores, in which one core is tapered to a larger dimension, so that all the cores are used as a composite input port, and the one larger core is used as an output port. In addition, transverse couplers can be fabricated in a similar fashion. The waveguide cores are preferably made of SiN. In some cases, a layer of SiN which is provided as an etch stop is used as at least one of the waveguide cores. The waveguide cores can be spaced away from a semiconductor layer so as to minimize loses.
    Type: Application
    Filed: November 13, 2018
    Publication date: March 28, 2019
    Inventors: Ari Novack, Ruizhi Shi, Michael J. Hochberg, Thomas Baehr-Jones
  • Patent number: 10222565
    Abstract: Two semiconductor chips are optically aligned to form a hybrid semiconductor device. Both chips have optical waveguides and alignment surface positioned at precisely-defined complementary vertical offsets from optical axes of the corresponding waveguides, so that the waveguides are vertically aligned when one of the chips is placed atop the other with their alignment surface abutting each other. The position of the at least one of the alignment surface in a layer stack of its chip is precisely defined by epitaxy. The chips are bonded at offset bonding pads with the alignment surfaces abutting in the absence of bonding material therebetween.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: March 5, 2019
    Assignee: Elenion Technologies, LLC
    Inventors: David Henry Kinghorn, Ari Jason Novack, Holger N. Klein, Nathan A. Nuttall, Kishor V. Desai, Daniel J. Blumenthal, Michael J. Hochberg, Ruizhi Shi
  • Patent number: 10215920
    Abstract: A low loss high extinction ratio on-chip polarizer is disclosed. The polarizer is formed of a mode convertor followed by a mode squeezer and a dump waveguide, and may be configured to pass a desired waveguide mode and reject undesired modes. An embodiment is described that transmits a TE0 mode while blocking a TM0 mode by converting it into a higher-order TEn mode in a waveguide taper, squeezing out the TEn mode in a second waveguide taper to lessen its confinement, and then dumping the TEn mode in a waveguide bend that is configured to pass the TE0 mode.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: February 26, 2019
    Assignee: Elenion Technologies, LLC
    Inventors: Yangjin Ma, Michael J. Hochberg, Ruizhi Shi, Yang Liu
  • Patent number: 10209465
    Abstract: A light shield may be formed in photonic integrated circuit between integrated optical devices of the photonic integrated circuit. The light shield may be built by using materials already present in the photonic integrated circuit, for example the light shield may include metal walls and doped semiconductor regions. Light-emitting or light-sensitive integrated optical devices or modules of a photonic integrated circuit may be constructed with light shields integrally built in.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: February 19, 2019
    Assignee: Elenion Technologies, LLC
    Inventors: Ruizhi Shi, Yang Liu, Ari Novack, Yangjin Ma, Kishore Padmaraju, Michael J. Hochberg
  • Publication number: 20190025508
    Abstract: A low loss high extinction ratio on-chip polarizer. The polarizer includes an input waveguide taper having an outer waveguiding region that widens in the direction of light propagation along at least a portion of the taper length, and a core waveguiding region that narrows in the direction of light propagation along at least a portion of the taper length, so as to selectively squeeze out light of undesired modes into the outer regions while preserving light of a desired mode in the waveguide core. An output filter section is provided to prevent light from reentering the output waveguide after being squeezed out. An integrated light absorber/deflector may be coupled to the outer waveguiding regions.
    Type: Application
    Filed: September 10, 2018
    Publication date: January 24, 2019
    Inventors: Ruizhi Shi, Thomas Wetteland Baehr-Jones, Yangjin Ma, Yang Liu, Michael J. Hochberg, Matthew Akio Streshinsky, Alexandre Horth
  • Patent number: 10185087
    Abstract: A compact, low-loss and wavelength insensitive Y-junction for submicron silicon waveguides. The design was performed using FDTD and particle swarm optimization (PSO). The device was fabricated in a 248 nm CMOS line. Measured average insertion loss is 0.28±0.02 dB across an 8-inch wafer. The device footprint is less than 1.2 ?m×2 ?m, orders of magnitude smaller than MMI and directional couplers.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: January 22, 2019
    Assignee: Elenion Technologies, LLC
    Inventors: Yang Liu, Yangjin Ma, Ruizhi Shi, Michael J. Hochberg, Yi Zhang, Shuyu Yang, Thomas Wetteland Baehr-Jones
  • Patent number: 10156678
    Abstract: A composite optical waveguide is constructed using an array of waveguide cores, in which one core is tapered to a larger dimension, so that all the cores are used as a composite input port, and the one larger core is used as an output port. In addition, transverse couplers can be fabricated in a similar fashion. The waveguide cores are preferably made of SiN. In some cases, a layer of SiN which is provided as an etch stop is used as at least one of the waveguide cores. The waveguide cores can be spaced away from a semiconductor layer so as to minimize loses.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: December 18, 2018
    Assignee: Elenion Technologies, LLC
    Inventors: Ari Novack, Ruizhi Shi, Michael J. Hochberg, Thomas Baehr-Jones
  • Publication number: 20180356593
    Abstract: An optical device and a method of manufacturing an optical device, including a ridge waveguide second, and a strip-loaded ridge waveguide section, comprises applying two different protective layers and two separate etches at two different depths. The protective layers overlap to protect the same section of the optical device, and to limit the surfaces of optical device to exposure to multiple etches, except at edges where the protective layers overlap.
    Type: Application
    Filed: June 13, 2017
    Publication date: December 13, 2018
    Inventors: Thomas Wetteland Baehr-Jones, Ruizhi Shi
  • Patent number: 10101533
    Abstract: An integrated optical device fabricated in the back end of line process located within the vertical span of the metal stack and having one or more advantages over a corresponding integrated optical device fabricated in the silicon on insulator layer.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: October 16, 2018
    Assignee: Elenion Technologies, LLC
    Inventors: Ruizhi Shi, Michael J. Hochberg, Ari Jason Novack, Thomas Wetteland Baehr-Jones
  • Publication number: 20180102440
    Abstract: A temperature-controlled photodetector sub-system is described. The temperature control element allows the operation of the photodetector at a desired temperature. The temperature control element can be a heater or a cooler. In some cases, the photodetector is a germanium photodetector. In some cases a temperature measuring device is provided. In some cases, a control circuit is used to control the temperature of the germanium photodetector within a temperature range, or at a temperature of interest. An advantage provided by the apparatus described is the operation of the photodetector so that the responsivity of the germanium detector can be held at essentially a constant value.
    Type: Application
    Filed: December 13, 2017
    Publication date: April 12, 2018
    Inventors: Ari Novack, Ruizhi Shi, Jean Claude Labarrie
  • Publication number: 20180088277
    Abstract: An integrated optical device fabricated in the back end of line process located within the vertical span of the metal stack and having one or more advantages over a corresponding integrated optical device fabricated in the silicon on insulator layer.
    Type: Application
    Filed: November 30, 2017
    Publication date: March 29, 2018
    Inventors: Ruizhi Shi, Michael J. Hochberg, Ari Jason Novack, Thomas Wetteland Baehr-Jones
  • Publication number: 20180081116
    Abstract: A compact, low-loss and wavelength insensitive Y-junction for submicron silicon waveguides. The design was performed using FDTD and particle swarm optimization (PSO). The device was fabricated in a 248 nm CMOS line. Measured average insertion loss is 0.28±0.02 dB across an 8-inch wafer. The device footprint is less than 1.2 ?m×2 ?m, orders of magnitude smaller than MMI and directional couplers.
    Type: Application
    Filed: November 29, 2017
    Publication date: March 22, 2018
    Inventors: Yang Liu, Yangjin Ma, Ruizhi Shi, Michael J. Hochberg, Yi Zhang, Shuyu Yang, Thomas Wetteland Baehr-Jones
  • Publication number: 20180052290
    Abstract: Two semiconductor chips are optically aligned to form a hybrid semiconductor device. Both chips have optical waveguides and alignment surface positioned at precisely-defined complementary vertical offsets from optical axes of the corresponding waveguides, so that the waveguides are vertically aligned when one of the chips is placed atop the other with their alignment surface abutting each other. The position of the at least one of the alignment surface in a layer stack of its chip is precisely defined by epitaxy. The chips are bonded at offset bonding pads with the alignment surfaces abutting in the absence of bonding material therebetween.
    Type: Application
    Filed: October 13, 2017
    Publication date: February 22, 2018
    Inventors: David Henry Kinghorn, Ari Jason Novack, Holger N. Klein, Nathan A. Nuttall, Kishor V. Desai, Daniel J. Blumenthal, Michael J. Hochberg, Ruizhi Shi
  • Publication number: 20180045887
    Abstract: A low loss high extinction ratio on-chip polarizer is disclosed. The polarizer includes an input waveguide taper having an outer waveguiding region that widens in the direction of light propagation along at least a portion of the taper length, and a core waveguiding region that narrows in the direction of light propagation along at least a portion of the taper length, so as to selectively squeeze out light of undesired modes into the outer regions while preserving light of a desired mode in the waveguide core. An integrated light absorber/deflector may be coupled to the outer waveguiding regions.
    Type: Application
    Filed: October 5, 2017
    Publication date: February 15, 2018
    Inventors: Ruizhi Shi, Thomas Wetteland Baehr-Jones, Yangjin Ma, Yang Liu, Michael J. Hochberg, Matthew Akio Streshinsky
  • Publication number: 20180039026
    Abstract: A composite optical waveguide is constructed using an array of waveguide cores, in which one core is tapered to a larger dimension, so that all the cores are used as a composite input port, and the one larger core is used as an output port. In addition, transverse couplers can be fabricated in a similar fashion. The waveguide cores are preferably made of SiN. In some cases, a layer of SiN which is provided as an etch stop is used as at least one of the waveguide cores. The waveguide cores can be spaced away from a semiconductor layer so as to minimize loses.
    Type: Application
    Filed: August 24, 2017
    Publication date: February 8, 2018
    Inventors: Ari Novack, Ruizhi Shi, Michael J. Hochberg, Thomas Baehr-Jones
  • Patent number: 9871153
    Abstract: A temperature-controlled photodetector sub-system is described. The temperature control element allows the operation of the photodetector at a desired temperature. The temperature control element can be a heater or a cooler. In some cases, the photodetector is a germanium photodetector. In some cases a temperature measuring device is provided. In some cases, a control circuit is used to control the temperature of the germanium photodetector within a temperature range, or at a temperature of interest. An advantage provided by the apparatus described is the operation of the photodetector so that the responsivity of the germanium detector can be held at essentially a constant value.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: January 16, 2018
    Assignee: Elenion Technologies, Inc.
    Inventors: Ari Novack, Ruizhi Shi, Jean Claude Labarrie
  • Patent number: 9851506
    Abstract: An integrated optical device fabricated in the back end of line process located within the vertical span of the metal stack and having one or more advantages over a corresponding integrated optical device fabricated in the silicon on insulator layer.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: December 26, 2017
    Assignee: Elenion Technologies, LLC
    Inventors: Ruizhi Shi, Michael J. Hochberg, Ari Jason Novack, Thomas Wetteland Baehr-Jones
  • Patent number: 9851503
    Abstract: A compact, low-loss and wavelength insensitive Y-junction for submicron silicon waveguides. The design was performed using FDTD and particle swarm optimization (PSO). The device was fabricated in a 248 nm CMOS line. Measured average insertion loss is 0.28±0.02 dB across an 8-inch wafer. The device footprint is less than 1.2 ?m×2 ?m, orders of magnitude smaller than MMI and directional couplers.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: December 26, 2017
    Assignee: Elenion Technologies, LLC
    Inventors: Yang Liu, Yangjin Ma, Ruizhi Shi, Michael J. Hochberg, Yi Zhang, Shuyu Yang, Thomas Wetteland Baehr-Jones
  • Publication number: 20170329082
    Abstract: A low loss high extinction ratio on-chip polarizer is disclosed. The polarizer is formed of a mode convertor followed by a mode squeezer and a dump waveguide, and may be configured to pass a desired waveguide mode and reject undesired modes. An embodiment is described that transmits a TE0 mode while blocking a TM0 mode by converting it into a higher-order TEn mode in a waveguide taper, squeezing out the TEn mode in a second waveguide taper to lessen its confinement, and then dumping the TEn mode in a waveguide bend that is configured to pass the TE0 mode.
    Type: Application
    Filed: July 25, 2017
    Publication date: November 16, 2017
    Inventors: Yangjin Ma, Michael J. Hochberg, Ruizhi Shi, Yang Liu