Patents by Inventor Russell T. Herrin
Russell T. Herrin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160060107Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a beam structure and an electrode on an insulator layer, remote from the beam structure. The method further includes forming at least one sacrificial layer over the beam structure, and remote from the electrode. The method further includes forming a lid structure over the at least one sacrificial layer and the electrode. The method further includes providing simultaneously a vent hole through the lid structure to expose the sacrificial layer and to form a partial via over the electrode. The method further includes venting the sacrificial layer to form a cavity. The method further includes sealing the vent hole with material. The method further includes forming a final via in the lid structure to the electrode, through the partial via.Type: ApplicationFiled: August 31, 2015Publication date: March 3, 2016Inventors: Russell T. HERRIN, Jeffrey C. MALING, Anthony K. STAMPER
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Publication number: 20160055282Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a beam structure and an electrode on an insulator layer, remote from the beam structure. The method further includes forming at least one sacrificial layer over the beam structure, and remote from the electrode. The method further includes forming a lid structure over the at least one sacrificial layer and the electrode. The method further includes providing simultaneously a vent hole through the lid structure to expose the sacrificial layer and to form a partial via over the electrode. The method further includes venting the sacrificial layer to form a cavity. The method further includes sealing the vent hole with material. The method further includes forming a final via in the lid structure to the electrode, through the partial via.Type: ApplicationFiled: August 31, 2015Publication date: February 25, 2016Inventors: Russell T. HERRIN, Jeffrey C. MALING, Anthony K. STAMPER
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Patent number: 8956903Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) cavity includes forming a first sacrificial cavity layer over a wiring layer and substrate. The method further includes forming an insulator layer over the first sacrificial cavity layer. The method further includes performing a reverse damascene etchback process on the insulator layer. The method further includes planarizing the insulator layer and the first sacrificial cavity layer. The method further includes venting or stripping of the first sacrificial cavity layer to a planar surface for a first cavity of the MEMS.Type: GrantFiled: December 20, 2010Date of Patent: February 17, 2015Assignee: International Business Machines CorporationInventors: Russell T. Herrin, Christopher V. Jahnes, Anthony K. Stamper, Eric J. White
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Publication number: 20150041932Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) cavity includes forming a first sacrificial cavity layer over a wiring layer and substrate. The method further includes forming an insulator layer over the first sacrificial cavity layer. The method further includes performing a reverse damascene etchback process on the insulator layer. The method further includes planarizing the insulator layer and the first sacrificial cavity layer. The method further includes venting or stripping of the first sacrificial cavity layer to a planar surface for a first cavity of the MEMS.Type: ApplicationFiled: October 16, 2014Publication date: February 12, 2015Inventors: Russell T. HERRIN, Christopher V. JAHNES, Anthony K. STAMPER, Eric J. WHITE
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Publication number: 20150035076Abstract: A structure that provides a diffusion barrier between two doped regions. The structure includes a diffusion barrier including a semiconductor layer comprising a first doped region and a second doped region; and a diffusion barrier separating the first doped region and the second doped region, wherein the diffusion barrier comprises a doped portion and a notch above the doped portion.Type: ApplicationFiled: October 17, 2014Publication date: February 5, 2015Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Russell T. Herrin, Laura J. Schutz, Steven M. Shank
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Patent number: 8932920Abstract: A self-aligned diffusion barrier may be formed by forming a first masking layer, having a vertical sidewall on a semiconductor layer, above a first portion of the semiconductor layer. A first spacer layer, including a spacer region on the vertical sidewall, may be formed above the semiconductor layer. A second portion of the semiconductor layer not covered by the first masking layer or the spacer region may then be doped. A second masking layer may then be formed over the first spacer layer and planarized to expose at least a portion of the spacer region. The spacer region may then be etched to form a notch exposing a third portion of the semiconductor layer. The third portion may then be doped with a barrier dopant. The first masking layer may be removed and a second spacer layer filling the notch may be formed. The first portion may then be doped.Type: GrantFiled: May 29, 2013Date of Patent: January 13, 2015Assignee: International Business Machines CorporationInventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Russell T. Herrin, Laura J. Schutz, Steven M. Shank
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Patent number: 8916952Abstract: A self-aligned bipolar transistor and method of fabricating the same are disclosed. In an embodiment, a substrate and an intrinsic base are provided, followed by a first oxide layer, and an extrinsic base over the first oxide layer. A first opening is formed, exposing a portion of a surface of the extrinsic base. Sidewall spacers are formed in the first opening, and a self-aligned oxide mask is selectively formed on the exposed surface of the extrinsic base. The spacers are removed, and using the self-aligned oxide mask, the exposed extrinsic base and the first oxide layer are etched to expose the intrinsic base layer, forming a first and a second slot. A silicon layer stripe is selectively grown on the exposed intrinsic and/or extrinsic base layers in each of the first and second slots, substantially filling the respective slot.Type: GrantFiled: January 23, 2014Date of Patent: December 23, 2014Assignee: International Business Machines CorporationInventors: Kevin K. Chan, David L. Harame, Russell T. Herrin, Qizhi Liu
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Publication number: 20140353759Abstract: A self-aligned diffusion barrier may be formed by forming a first masking layer, having a vertical sidewall on a semiconductor layer, above a first portion of the semiconductor layer. A first spacer layer, including a spacer region on the vertical sidewall, may be formed above the semiconductor layer. A second portion of the semiconductor layer not covered by the first masking layer or the spacer region may then be doped. A second masking layer may then be formed over the first spacer layer and planarized to expose at least a portion of the spacer region. The spacer region may then be etched to form a notch exposing a third portion of the semiconductor layer. The third portion may then be doped with a barrier dopant. The first masking layer may be removed and a second spacer layer filling the notch may be formed. The first portion may then be doped.Type: ApplicationFiled: May 29, 2013Publication date: December 4, 2014Applicant: International Business Machines CorporationInventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Russell T. Herrin, Laura J. Schutz, Steven M. Shank
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Patent number: 8796130Abstract: A method patterns a polysilicon gate over two immediately adjacent, opposite polarity transistor devices. The method patterns a mask over the polysilicon gate. The mask has an opening in a location where the opposite polarity transistor devices abut one another. The method then removes some (a portion) of the polysilicon gate through the opening to form at least a partial recess (or potentially a complete opening) in the polysilicon gate. The recess separates the polysilicon gate into a first polysilicon gate and a second polysilicon gate. After forming the recess, the method dopes the first polysilicon gate using a first polarity dopant and dopes the second polysilicon gate using a second polarity dopant having an opposite polarity of the first polarity dopant.Type: GrantFiled: January 18, 2012Date of Patent: August 5, 2014Assignee: International Business Machines CorporationInventors: Jeffrey P. Gambino, Russell T. Herrin, Mark D. Jaffe, Laura J. Schutz
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Patent number: 8796058Abstract: Micro-Electro-Mechanical System (MEMS) structures, metrology structures and methods of manufacture are disclosed. The method includes forming one or metrology structure, during formation of a device in a chip area. The method further includes venting the one or more metrology structure after formation of the device.Type: GrantFiled: November 2, 2011Date of Patent: August 5, 2014Assignee: International Business Machines CorporationInventors: Russell T. Herrin, Daniel R. Miga, Anthony K. Stamper
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Publication number: 20140131773Abstract: A self-aligned bipolar transistor and method of fabricating the same are disclosed. In an embodiment, a substrate and an intrinsic base are provided, followed by a first oxide layer, and an extrinsic base over the first oxide layer. A first opening is formed, exposing a portion of a surface of the extrinsic base. Sidewall spacers are formed in the first opening, and a self-aligned oxide mask is selectively formed on the exposed surface of the extrinsic base. The spacers are removed, and using the self-aligned oxide mask, the exposed extrinsic base and the first oxide layer are etched to expose the intrinsic base layer, forming a first and a second slot. A silicon layer stripe is selectively grown on the exposed intrinsic and/or extrinsic base layers in each of the first and second slots, filling the respective slot.Type: ApplicationFiled: January 23, 2014Publication date: May 15, 2014Applicant: International Business Machines CorporationInventors: Kevin K. Chan, David L. Harame, Russell T. Herrin, Qizhi Liu
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Patent number: 8716096Abstract: A self-aligned bipolar transistor and method of fabricating the same are disclosed. In an embodiment, a substrate and an intrinsic base are provided, followed by a first oxide layer, and an extrinsic base over the first oxide layer. A first opening is formed, exposing a portion of a surface of the extrinsic base. Sidewall spacers are formed in the first opening, and a self-aligned oxide mask is selectively formed on the exposed surface of the extrinsic base. The spacers are removed, and using the self-aligned oxide mask, the exposed extrinsic base and the first oxide layer are etched to expose the intrinsic base layer, forming a first and a second slot. A silicon layer stripe is selectively grown on the exposed intrinsic and/or extrinsic base layers in each of the first and second slots, substantially filling the respective slot.Type: GrantFiled: December 13, 2011Date of Patent: May 6, 2014Assignee: International Business Machines CorporationInventors: Kevin K. Chan, David L. Harame, Russell T. Herrin, Qizhi Liu
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Patent number: 8673726Abstract: Disclosed are embodiments of a bipolar or heterojunction bipolar transistor and a method of forming the transistor. The transistor can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method allows for self-aligning of the emitter to base regions and incorporates the use of a sacrificial dielectric layer, which must be thick enough to withstand etch and cleaning processes and still remain intact to function as an etch stop layer when the conductive strap is subsequently formed. A chemically enhanced high pressure, low temperature oxidation (HIPOX) process can be used to form such a sacrificial dielectric layer.Type: GrantFiled: February 8, 2013Date of Patent: March 18, 2014Assignee: International Business Machines CorporationInventors: David L. Harame, Russell T. Herrin, Qizhi Liu
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Patent number: 8513084Abstract: Disclosed are embodiments of a bipolar or heterojunction bipolar transistor and a method of forming the transistor. The transistor can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method allows for self-aligning of the emitter to base regions and incorporates the use of a sacrificial dielectric layer, which must be thick enough to withstand etch and cleaning processes and still remain intact to function as an etch stop layer when the conductive strap is subsequently formed. A chemically enhanced high pressure, low temperature oxidation (HIPOX) process can be used to form such a sacrificial dielectric layer.Type: GrantFiled: December 14, 2010Date of Patent: August 20, 2013Assignee: International Business Machines CorporationInventors: David L. Harame, Russell T. Herrin, Qizhi Liu
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Publication number: 20130181293Abstract: A method patterns a polysilicon gate over two immediately adjacent, opposite polarity transistor devices. The method patterns a mask over the polysilicon gate. The mask has an opening in a location where the opposite polarity transistor devices abut one another. The method then removes some (a portion) of the polysilicon gate through the opening to form at least a partial recess (or potentially a complete opening) in the polysilicon gate. The recess separates the polysilicon gate into a first polysilicon gate and a second polysilicon gate. After forming the recess, the method dopes the first polysilicon gate using a first polarity dopant and dopes the second polysilicon gate using a second polarity dopant having an opposite polarity of the first polarity dopant.Type: ApplicationFiled: January 18, 2012Publication date: July 18, 2013Applicant: International Business Machines CorporationInventors: Jeffrey P. Gambino, Russell T. Herrin, Mark D. Jaffe, Laura J. Schutz
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Publication number: 20130146947Abstract: A self-aligned bipolar transistor and method of fabricating the same are disclosed. In an embodiment, a substrate and an intrinsic base are provided, followed by a first oxide layer, and an extrinsic base over the first oxide layer. A first opening is formed, exposing a portion of a surface of the extrinsic base. Sidewall spacers are formed in the first opening, and a self-aligned oxide mask is selectively formed on the exposed surface of the extrinsic base. The spacers are removed, and using the self-aligned oxide mask, the exposed extrinsic base and the first oxide layer are etched to expose the intrinsic base layer, forming a first and a second slot. A silicon layer stripe is selectively grown on the exposed intrinsic and/or extrinsic base layers in each of the first and second slots, substantially filling the respective slot.Type: ApplicationFiled: December 13, 2011Publication date: June 13, 2013Applicant: International Business Machines CorporationInventors: Kevin K. Chan, David L. Harame, Russell T. Herrin, Qizhi Liu
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Publication number: 20130105920Abstract: Micro-Electro-Mechanical System (MEMS) structures, metrology structures and methods of manufacture are disclosed. The method includes forming one or metrology structure, during formation of a device in a chip area. The method further includes venting the one or more metrology structure after formation of the device.Type: ApplicationFiled: November 2, 2011Publication date: May 2, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Russell T. HERRIN, Daniel R. MIGA, Anthony K. STAMPER
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Patent number: 8405186Abstract: Disclosed are embodiments of an improved transistor structure (e.g., a bipolar transistor (BT) structure or heterojunction bipolar transistor (HBT) structure) and a method of forming the transistor structure. The structure embodiments can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method embodiments allow for self-aligning of the emitter to base regions and further allow the geometries of different features (e.g., the thickness of the dielectric layer, the width of the conductive strap, the width of the dielectric spacer and the width of the emitter layer) to be selectively adjusted in order to optimize transistor performance.Type: GrantFiled: June 17, 2010Date of Patent: March 26, 2013Assignee: International Business Machines CorporationInventors: Renata Camillo-Castillo, Mattias E. Dahlstrom, Peter B. Gray, David L. Harame, Russell T. Herrin, Alvin J. Joseph, Andreas D. Stricker
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Publication number: 20110316097Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) cavity includes forming a first sacrificial cavity layer over a wiring layer and substrate. The method further includes forming an insulator layer over the first sacrificial cavity layer. The method further includes performing a reverse damascene etchback process on the insulator layer. The method further includes planarizing the insulator layer and the first sacrificial cavity layer. The method further includes venting or stripping of the first sacrificial cavity layer to a planar surface for a first cavity of the MEMS.Type: ApplicationFiled: December 20, 2010Publication date: December 29, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Russell T. HERRIN, Christopher V. JAHNES, Anthony K. STAMPER, Eric J. WHITE
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Publication number: 20110315528Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a beam structure and an electrode on an insulator layer, remote from the beam structure. The method further includes forming at least one sacrificial layer over the beam structure, and remote from the electrode. The method further includes forming a lid structure over the at least one sacrificial layer and the electrode. The method further includes providing simultaneously a vent hole through the lid structure to expose the sacrificial layer and to form a partial via over the electrode. The method further includes venting the sacrificial layer to form a cavity. The method further includes sealing the vent hole with material. The method further includes forming a final via in the lid structure to the electrode, through the partial via.Type: ApplicationFiled: December 23, 2010Publication date: December 29, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Russell T. HERRIN, Jeffrey C. Maling, Anthony K. Stamper