Patents by Inventor Ryan Scott Haraden
Ryan Scott Haraden has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10242654Abstract: Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power.Type: GrantFiled: January 25, 2017Date of Patent: March 26, 2019Assignee: Microsoft Technology Licensing, LLCInventors: Tolga Ozguner, Jeffrey Powers Bradford, Miguel Comparan, Gene Leung, Adam James Muff, Ryan Scott Haraden, Christopher Jon Johnson
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Publication number: 20190050149Abstract: Techniques for controlling access to a memory are provided. The techniques may include receiving and storing output pixel data in a buffer, providing the stored output pixel data to a display controller, receiving stored output pixel data from the buffer at the display controller, switching to a second operating mode state based at least on an amount of available data in the buffer being less than or equal to a threshold, identifying a portion of the image data stored in a memory device for use in generating output pixel data for an updated image, and, in response to operating in the second operating mode, generating the output pixel data without issuing a memory read command via an interconnect to retrieve the portion of the initial image while operating in the second operating mode, and providing the output pixel data to the buffer.Type: ApplicationFiled: October 8, 2018Publication date: February 14, 2019Applicant: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Tolga OZGUNER, Ishan Jitendra BHATT, Miguel COMPARAN, Ryan Scott HARADEN, Jeffrey Powers BRADFORD, Gene LEUNG
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Patent number: 10181175Abstract: Methods for preprocessing pixel data using a Direct Memory Access (DMA) engine during a data transfer of the pixel data from a first memory (e.g., a DRAM) to a second memory (e.g., an SRAM) are described. The pixel data may derive from a color camera or a depth camera in which individual pixel values are not a multiple of eight bits. In some cases, the DMA engine may perform a variety of image processing operations on the pixel data prior to the pixel data being written into the second memory. In one embodiment, the DMA engine may be configured to determine whether one or more pixels corresponding with the pixel data may be invalidated or skipped based on a minimum pixel value threshold and a maximum pixel value threshold and to embed pixel skipping information within unused bits of the pixel data.Type: GrantFiled: December 17, 2014Date of Patent: January 15, 2019Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Ryan Scott Haraden, Matthew Ray Tubbs, Adam James Muff, Robert Allen Shearer
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Publication number: 20180322688Abstract: Systems and methods for multistage post-rendering image transformation are provided. The system may include a transform generation module arranged to dynamically generate an image transformation. The system may include a transform data generation module arranged to generate first and second transformation data by applying the generated image transformation for first and second sampling positions and storing the transformation data in a memory. The system may include a first image transformation stage that selects the first and second transformation data for a destination image position and calculates an estimated source image position based on the selected first and second transformation data.Type: ApplicationFiled: May 3, 2017Publication date: November 8, 2018Applicant: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Tolga OZGUNER, Miguel COMPARAN, Ryan Scott HARADEN, Jeffrey Powers BRADFORD
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Publication number: 20180301125Abstract: Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data and multiple LSR processing engines.Type: ApplicationFiled: April 12, 2017Publication date: October 18, 2018Inventors: Ryan Scott Haraden, Tolga Ozguner, Adam James Muff, Jeffrey Powers Bradford, Christopher Jon Johnson, Gene Leung, Miguel Comparan
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Patent number: 10095408Abstract: Systems and methods for controlling access to a memory are provided. The system may include a buffer to store output data generated by a processing module, and provide the output data to a real-time module, and a buffer monitoring circuit to output an underflow approaching state indication in response to an amount of available data in the buffer being less than or equal to a threshold. The system may include a memory access module arranged to receive memory requests issued by the processing module, and configured to, while operating in a first mode, respond to memory requests with corresponding data retrieved from the memory, switch to operating in a second mode in response to receiving the underflow approaching state indication, and in response to operating in the second mode, respond to memory requests indicating the memory access module did not attempt to retrieve corresponding data from the memory.Type: GrantFiled: March 10, 2017Date of Patent: October 9, 2018Assignee: Microsoft Technology Licensing, LLCInventors: Tolga Ozguner, Ishan Jitendra Bhatt, Miguel Comparan, Ryan Scott Haraden, Jeffrey Powers Bradford, Gene Leung
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Publication number: 20180276824Abstract: Optimizations are provided for late stage reprojection processing for a multi-layered scene. A scene is generated, which is based on a predicted pose of a portion of a computer system. A sub-region is identified within one of the layers and is isolated from the other regions in the scene. Thereafter, late stage reprojection processing is applied to that sub-region selectively/differently than other regions in the scene that do not undergo the same late state reprojection processing.Type: ApplicationFiled: March 27, 2017Publication date: September 27, 2018Inventors: Ryan Scott Haraden, Jeffrey Powers Bradford, Miguel Comparan, Adam James Muff, Gene Leung, Tolga Ozguner
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Publication number: 20180275748Abstract: Optimizations are provided for late stage reprojection processing for a multi-layered scene. A multi-layered scene is generated. Late stage reprojection processing is applied to a first layer and different late stage reprojection processing is applied to a second layer. The late stage reprojection processing that is applied to the second layer includes one or more transformations that are applied to the second layer. After the late stage reprojection processing on the various layers is complete, a unified layer is created by compositing the layers together. Then, the render the unified layer is rendered.Type: ApplicationFiled: March 27, 2017Publication date: September 27, 2018Inventors: Ryan Scott Haraden, Jeffrey Powers Bradford, Miguel Comparan, Adam James Muff, Gene Leung, Tolga Ozguner
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Publication number: 20180260120Abstract: Systems and methods for controlling access to a memory are provided. The system may include a buffer to store output data generated by a processing module, and provide the output data to a real-time module, and a buffer monitoring circuit to output an underflow approaching state indication in response to an amount of available data in the buffer being less than or equal to a threshold. The system may include a memory access module arranged to receive memory requests issued by the processing module, and configured to, while operating in a first mode, respond to memory requests with corresponding data retrieved from the memory, switch to operating in a second mode in response to receiving the underflow approaching state indication, and in response to operating in the second mode, respond to memory requests indicating the memory access module did not attempt to retrieve corresponding data from the memory.Type: ApplicationFiled: March 10, 2017Publication date: September 13, 2018Applicant: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Tolga Ozguner, Ishan Jitendra Bhatt, Miguel Comparan, Ryan Scott Haraden, Jeffrey Powers Bradford, Gene Leung
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Publication number: 20180260931Abstract: Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data.Type: ApplicationFiled: May 15, 2018Publication date: September 13, 2018Inventors: Tolga OZGUNER, Gene LEUNG, Jeffrey Powers BRADFORD, Adam James MUFF, Miguel COMPARAN, Ryan Scott HARADEN, Christopher Jon JOHNSON
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Publication number: 20180211638Abstract: Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power.Type: ApplicationFiled: January 25, 2017Publication date: July 26, 2018Inventors: Tolga Ozguner, Jeffrey Powers Bradford, Miguel Comparan, Gene Leung, Adam James Muff, Ryan Scott Haraden, Christopher Jon Johnson
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Patent number: 9978118Abstract: Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data.Type: GrantFiled: January 25, 2017Date of Patent: May 22, 2018Assignee: Microsoft Technology Licensing, LLCInventors: Tolga Ozguner, Gene Leung, Jeffrey Powers Bradford, Adam James Muff, Miguel Comparan, Ryan Scott Haraden, Christopher Jon Johnson
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Patent number: 9710878Abstract: Methods for preprocessing pixel data using a Direct Memory Access (DMA) engine during a data transfer of the pixel data from a first memory (e.g., a DRAM) to a second memory (e.g., a local cache) are described. The pixel data may derive from an image capturing device (e.g., a color camera or a depth camera) in which individual pixel values are not a multiple of eight bits. In some embodiments, the DMA engine may perform a variety of image processing operations on the pixel data prior to the pixel data being written into the second memory. In one example, the DMA engine may be configured to identify and label one or more pixels as being within a particular range of pixel values and/or the DMA engine may be configured to label pixels as belonging to one or more pixel groups based on their pixel values.Type: GrantFiled: December 17, 2014Date of Patent: July 18, 2017Assignee: MICROSOFT TECHNOLOY LICENSING, LLCInventors: Ryan Scott Haraden, Matthew Ray Tubbs, Adam James Muff, Robert Allen Shearer
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Publication number: 20160180494Abstract: Methods for preprocessing pixel data using a Direct Memory Access (DMA) engine during a data transfer of the pixel data from a first memory (e.g., a DRAM) to a second memory (e.g., an SRAM) are described. The pixel data may derive from a color camera or a depth camera in which individual pixel values are not a multiple of eight bits. In some cases, the DMA engine may perform a variety of image processing operations on the pixel data prior to the pixel data being written into the second memory. In one embodiment, the DMA engine may be configured to determine whether one or more pixels corresponding with the pixel data may be invalidated or skipped based on a minimum pixel value threshold and a maximum pixel value threshold and to embed pixel skipping information within unused bits of the pixel data.Type: ApplicationFiled: December 17, 2014Publication date: June 23, 2016Inventors: Ryan Scott Haraden, Matthew Ray Tubbs, Adam James Muff, Robert Allen Shearer
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Publication number: 20160180493Abstract: Methods for preprocessing pixel data using a Direct Memory Access (DMA) engine during a data transfer of the pixel data from a first memory (e.g., a DRAM) to a second memory (e.g., a local cache) are described. The pixel data may derive from an image capturing device (e.g., a color camera or a depth camera) in which individual pixel values are not a multiple of eight bits. In some embodiments, the DMA engine may perform a variety of image processing operations on the pixel data prior to the pixel data being written into the second memory. In one example, the DMA engine may be configured to identify and label one or more pixels as being within a particular range of pixel values and/or the DMA engine may be configured to label pixels as belonging to one or more pixel groups based on their pixel values.Type: ApplicationFiled: December 17, 2014Publication date: June 23, 2016Inventors: Ryan Scott Haraden, Matthew Ray Tubbs, Adam James Muff, Robert Allen Shearer
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Patent number: 8549217Abstract: A periodic command spacing mechanism is provided for spacing periodic commands (e.g., refresh commands, ZQ calibration, etc.) to a volatile memory (e.g., SDRAM, DRAM, EDRAM, etc.) for increased performance and decreased collision. In one embodiment, periodic command requests are monitored and if a collision is detected between two or more of the requests, the colliding requests are spaced with respect to one another by a timer offset applied on a chip select basis. The periodic command spacing mechanism may be used in conjunction with command arbitration to make sure the periodic commands are executed without significantly impacting performance (e.g., Reads and Writes are allowed to flow). Preferably, the periodic command requests are initialized by generating an initial sequence of individual requests, each successive request in the initial sequence being generated spaced apart with respect to the previous request by a timer offset applied on a chip select basis.Type: GrantFiled: November 17, 2009Date of Patent: October 1, 2013Assignee: International Business Machines CorporationInventors: Herman Lee Blackmon, Ronald Ernest Freking, Ryan Scott Haraden, Joseph Allen Kirscht
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Patent number: 8006013Abstract: The disclosure relates to a method and apparatus to efficiently address livelock in a multi-processor system. In one embodiment, the disclosure is directed to a method for preventing a system bus livelock in a system having a plurality of processors communicating respectively through a plurality of bus masters to a plurality of IO Controllers across a system bus by: receiving at an MMIO state machine a plurality of snoop commands issued from the plurality of processors, identifying a first processor and a second processor from the plurality of processors, each of the first processor and the second processor having a first number of snoop commands in the input queue and a second number of responses in the output queue, the first number and the second number exceeding a threshold; issuing a burst prevention response to the first processor and the second process.Type: GrantFiled: August 7, 2008Date of Patent: August 23, 2011Assignee: International Business Machines CorporationInventors: Benjamin Lee Goodman, Ryan Scott Haraden
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Publication number: 20110119439Abstract: A periodic command spacing mechanism is provided for spacing periodic commands (e.g., refresh commands, ZQ calibration, etc.) to a volatile memory (e.g., SDRAM, DRAM, EDRAM, etc.) for increased performance and decreased collision. In one embodiment, periodic command requests are monitored and if a collision is detected between two or more of the requests, the colliding requests are spaced with respect to one another by a timer offset applied on a chip select basis. The periodic command spacing mechanism may be used in conjunction with command arbitration to make sure the periodic commands are executed without significantly impacting performance (e.g., Reads and Writes are allowed to flow). Preferably, the periodic command requests are initialized by generating an initial sequence of individual requests, each successive request in the initial sequence being generated spaced apart with respect to the previous request by a timer offset applied on a chip select basis.Type: ApplicationFiled: November 17, 2009Publication date: May 19, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Herman Lee Blackmon, Ronald Ernest Freking, Ryan Scott Haraden, Joseph Allen Kirscht
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Patent number: 7941633Abstract: A computer implemented method, apparatus and program product automatically optimizes hash function operation by recognizing when a first hash function results in an unacceptable number of cache misses, and by dynamically trying another hash function to determine which hash function results in the most cache hits. In this manner, hardware optimizes hash function operation in the face of changing loads and associated data flow patterns.Type: GrantFiled: December 18, 2007Date of Patent: May 10, 2011Assignee: International Business Machines CorporationInventors: Marcy Evelyn Byers, Ronald Ernest Freking, Ryan Scott Haraden, David Alan Shedivy
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Patent number: 7681003Abstract: An adapter includes registers, a local context table, and logic that allows copying hardware context structures from a first location in memory to a second location in memory while the computer system continues to run. The local context table in the adapter is loaded with a desired block of context entries from the first location in memory. Values in the registers cause the adapter to write this desired block of context entries to the second location in memory in a way that does not inhibit the operation of the computer system.Type: GrantFiled: June 5, 2008Date of Patent: March 16, 2010Assignee: International Business Machines CorporationInventors: Ronald Edward Fuhs, Ryan Scott Haraden, Bruce Marshall Walk