Abstract: The disclosure relates to a method and apparatus to efficiently address livelock in a multi-processor system. In one embodiment, the disclosure is directed to a method for preventing a system bus livelock in a system having a plurality of processors communicating respectively through a plurality of bus masters to a plurality of IO Controllers across a system bus by: receiving at an MMIO state machine a plurality of snoop commands issued from the plurality of processors, identifying a first processor and a second processor from the plurality of processors, each of the first processor and the second processor having a first number of snoop commands in the input queue and a second number of responses in the output queue, the first number and the second number exceeding a threshold; issuing a burst prevention response to the first processor and the second process.

Abstract: A computer implemented method, apparatus and program product automatically optimizes hash function operation by recognizing when a first hash function results in an unacceptable number of cache misses, and by dynamically trying another hash function to determine which hash function results in the most cache hits. In this manner, hardware optimizes hash function operation in the face of changing loads and associated data flow patterns.

Abstract: An adapter includes registers, a local context table, and logic that allows copying hardware context structures from a first location in memory to a second location in memory while the computer system continues to run. The local context table in the adapter is loaded with a desired block of context entries from the first location in memory. Values in the registers cause the adapter to write this desired block of context entries to the second location in memory in a way that does not inhibit the operation of the computer system.

Abstract: An adapter includes registers, a local context table, and logic that allows copying hardware context structures from a first location in memory to a second location in memory while the computer system continues to run. The local context table in the adapter is loaded with a desired block of context entries from the first location in memory. Values in the registers cause the adapter to write this desired block of context entries to the second location in memory in a way that does not inhibit the operation of the computer system.

Abstract: Concurrent read access and exclusive write access are provided in a shared memory architecture to permit one or more devices in the shared memory architecture to maintain read access to a block of memory such as a cache line while one device has exclusive permission to modify that block of memory. By doing so, a device that has permission to modify may make updates to its copy of the block of memory without invalidating other copies of the block of memory, and potentially enabling other devices to continue to read data from their respective copies of the block of memory without having to retrieve the updated copy of the block of memory.