Patents by Inventor Ryo Tsuda

Ryo Tsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240096182
    Abstract: An action detection system (10) includes an action specification unit (18) configured to start specification of at least one action ID based on at least part of skeleton information extracted from video data that is a captured video of a user in response to detection of the user visiting checkout machine determined in advance, a determination unit (20) configured to determine whether or not an action sequence including the specified at least one action ID corresponds to registration action sequences registered in advance, and a processing control unit (21) configured to execute processing determined in advance in accordance with a determination result.
    Type: Application
    Filed: July 28, 2021
    Publication date: March 21, 2024
    Applicant: NEC Corporation
    Inventors: Ryo KAWAI, Noboru YOSHIDA, Jianquan LIU, Shunsuke TSUDA, Yuki TSURUOKA
  • Patent number: 11488896
    Abstract: An object is to provide a technique capable of enhancing electrical characteristics and reliability of a semiconductor device. The semiconductor device includes a plurality of semiconductor chips, a plurality of electrodes each being electrically connected to each of the plurality of semiconductor chips, a sealing member, and a joint part. The sealing member covers the plurality of semiconductor chips, and parts being connected to the plurality of semiconductor chips, of the plurality of electrodes. The joint part is disposed outside the sealing member to electrically connect parts which are not covered by the sealing member, of the plurality of electrodes.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: November 1, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yukimasa Hayashida, Shigeru Hasegawa, Ryo Tsuda, Ryutaro Date, Junichi Nakashima
  • Publication number: 20220301999
    Abstract: An insulated substrate (2) includes first and second circuit patterns (5,4). A semiconductor device (7) includes first and second main electrodes (9,8) connected to the first and second circuit patterns (5,4) respectively and through which main currents flow. A first lead (12) is solder jointed to the first circuit pattern (5). A second lead (11) is ultrasonic jointed to the second circuit pattern (4).
    Type: Application
    Filed: December 10, 2019
    Publication date: September 22, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventor: Ryo TSUDA
  • Patent number: 11063025
    Abstract: Gates of a plurality of semiconductor switching elements are electrically connected to a common gate control pattern by gate wires. Sources of the plurality of semiconductor switching elements are electrically connected to a common source control pattern by source wires. The gate control pattern is disposed to interpose the source control pattern between the gate control pattern and each of the plurality of semiconductor switching elements that are connected in parallel and that operate in parallel. Hence, each of the gate wires becomes longer than each of the source wires, and has an inductance larger than the source wire. Accordingly, gate oscillation is reduced or suppressed in the plurality of semiconductor switching elements that are connected in parallel and that operate in parallel.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: July 13, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Junichi Nakashima, Shota Morisaki, Yoshiko Tamada, Yasushi Nakayama, Tetsu Negishi, Ryo Tsuda, Yukimasa Hayashida, Ryutaro Date
  • Patent number: 10804253
    Abstract: First and second circuit patterns (5,6) are provided on an insulating substrate (1). First and second semiconductor chips (7,8) are provided on the first circuit pattern (5). A relay circuit pattern (10) is provided between the first semiconductor chip (7) and the second semiconductor chip (8) on the insulating substrate (1). A wire (11) is continuously connected to the first semiconductor chip (7), the relay circuit pattern (10), the second semiconductor chip (8) and the second circuit pattern (6) which are sequentially arranged in one direction.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: October 13, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yukimasa Hayashida, Ryo Tsuda, Ryutaro Date
  • Publication number: 20200185359
    Abstract: Gates of a plurality of semiconductor switching elements are electrically connected to a common gate control pattern by gate wires. Sources of the plurality of semiconductor switching elements are electrically connected to a common source control pattern by source wires. The gate control pattern is disposed to interpose the source control pattern between the gate control pattern and each of the plurality of semiconductor switching elements that are connected in parallel and that operate in parallel. Hence, each of the gate wires becomes longer than each of the source wires, and has an inductance larger than the source wire. Accordingly, gate oscillation is reduced or suppressed in the plurality of semiconductor switching elements that are connected in parallel and that operate in parallel.
    Type: Application
    Filed: August 27, 2018
    Publication date: June 11, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Junichi NAKASHIMA, Shota MORISAKI, Yoshiko TAMADA, Yasushi NAKAYAMA, Tetsu NEGISHI, Ryo TSUDA, Yukimasa HAYASHIDA, Ryutaro DATE
  • Publication number: 20200111772
    Abstract: First and second circuit patterns (5,6) are provided on an insulating substrate (1). First and second semiconductor chips (7,8) are provided on the first circuit pattern (5). A relay circuit pattern (10) is provided between the first semiconductor chip (7) and the second semiconductor chip (8) on the insulating substrate (1). A wire (11) is continuously connected to the first semiconductor chip (7), the relay circuit pattern (10), the second semiconductor chip (8) and the second circuit pattern (6) which are sequentially arranged in one direction.
    Type: Application
    Filed: August 10, 2016
    Publication date: April 9, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yukimasa HAYASHIDA, Ryo TSUDA, Ryutaro DATE
  • Patent number: 10361136
    Abstract: It is an object of the present invention to provide a semiconductor device which allows an increase in the number of semiconductor elements mounted in parallel and prevents a shape of an insulating substrate onto which the semiconductor elements are mounted, from being laterally long, and provide a semiconductor module including such semiconductor device. A semiconductor device according to the present invention includes an insulating substrate, a metal pattern which is a continuous piece and is bonded to one main surface of the insulating substrate, and a plurality of switching elements which are bonded to a surface opposite to the insulating substrate on the metal pattern, and the plurality of switching elements are arranged in a matrix of two or more rows and two or more columns on the metal pattern.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: July 23, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shigeru Hasegawa, Isao Umezaki, Ryo Tsuda, Yukimasa Hayashida, Ryutaro Date
  • Patent number: 10325827
    Abstract: A base plate, and a plurality of unit structures formed on the base plate are provided. Each of the unit structures including an insulating substrate fixed on the base plate, a metal pattern formed on the insulating substrate, a semiconductor element electrically connected to the metal pattern, and a main electrode having an upper end portion exposed to the outside and a lower end portion connected to a peripheral portion of the metal pattern closest to an outer edge of the base plate.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: June 18, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shigeru Hasegawa, Kazuhiro Morishita, Ryo Tsuda, Yukimasa Hayashida, Goro Yasutomi, Ryutaro Date
  • Publication number: 20180204778
    Abstract: It is an object of the present invention to provide a semiconductor device which allows an increase in the number of semiconductor elements mounted in parallel and prevents a shape of an insulating substrate onto which the semiconductor elements are mounted, from being laterally long, and provide a semiconductor module including such semiconductor device. A semiconductor device according to the present invention includes an insulating substrate, a metal pattern which is a continuous piece and is bonded to one main surface of the insulating substrate, and a plurality of switching elements which are bonded to a surface opposite to the insulating substrate on the metal pattern, and the plurality of switching elements are arranged in a matrix of two or more rows and two or more columns on the metal pattern.
    Type: Application
    Filed: September 29, 2015
    Publication date: July 19, 2018
    Applicant: Mitsubishi Electric Corporation
    Inventors: Shigeru HASEGAWA, Isao UMEZAKI, Ryo TSUDA, Yukimasa HAYASHIDA, Ryutaro DATE
  • Publication number: 20180197813
    Abstract: An object is to provide a technique capable of enhancing electrical characteristics and reliability of a semiconductor device. The semiconductor device includes a plurality of semiconductor chips, a plurality of electrodes each being electrically connected to each of the plurality of semiconductor chips, a sealing member, and a joint part. The sealing member covers the plurality of semiconductor chips, and parts being connected to the plurality of semiconductor chips, of the plurality of electrodes. The joint part is disposed outside the sealing member to electrically connect parts which are not covered by the sealing member, of the plurality of electrodes.
    Type: Application
    Filed: September 28, 2015
    Publication date: July 12, 2018
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yukimasa HAYASHIDA, Shigeru HASEGAWA, Ryo TSUDA, Ryutaro DATE, Junichi NAKASHIMA
  • Patent number: 9622368
    Abstract: Each of semiconductor module includes a semiconductor chip, a case surrounding the semiconductor chip, and a main electrode connected to the semiconductor chip and led out to an upper surface of case. A connecting electrode is connected and fixed to the main electrodes of the adjacent semiconductor modules. The connecting electrode is formed only of a metal plate.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: April 11, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ryo Tsuda, Kazuhiro Morishita
  • Publication number: 20160079142
    Abstract: A base plate, and a plurality of unit structures formed on the base plate are provided. Each of the unit structures including an insulating substrate fixed on the base plate, a metal pattern formed on the insulating substrate, a semiconductor element electrically connected to the metal pattern, and a main electrode having an upper end portion exposed to the outside and a lower end portion connected to a peripheral portion of the metal pattern closest to an outer edge of the base plate.
    Type: Application
    Filed: May 29, 2013
    Publication date: March 17, 2016
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Shigeru HASEGAWA, Kazuhiro MORISHITA, Ryo TSUDA, Yukimasa HAYASHIDA, Goro YASUTOMI, Ryutaro DATE
  • Publication number: 20150138733
    Abstract: Each of semiconductor module includes a semiconductor chip, a case surrounding the semiconductor chip, and a main electrode connected to the semiconductor chip and led out to an upper surface of case. A connecting electrode is connected and fixed to the main electrodes of the adjacent semiconductor modules. The connecting electrode is formed only of a metal plate. The rated current, the rated voltage and the circuit configuration can easily be changed by changing the connection using the connecting electrode, thus enabling reduction of the design time and facilitating manufacture management. Only a malfunctioning one of the semiconductor modules may be replaced. There is, therefore, no need to replace the entire device. The connecting electrode is formed of an electrically conductive plate and, therefore, enables reduction of the number of component parts and reduction of the device in size in comparison with the conventional wiring bus bar.
    Type: Application
    Filed: August 24, 2012
    Publication date: May 21, 2015
    Applicant: Mitsubishi Electric Corporation
    Inventors: Ryo Tsuda, Kazuhiro Morishita
  • Patent number: D790491
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: June 27, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yukimasa Hayashida, Shinichi Iura, Hitoshi Uemura, Daisuke Oya, Kenji Hatori, Yasuhiro Sakai, Ryo Tsuda, Ryutaro Date
  • Patent number: D798832
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: October 3, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yukimasa Hayashida, Shinichi Iura, Hitoshi Uemura, Daisuke Oya, Kenji Hatori, Yasuhiro Sakai, Ryo Tsuda, Ryutaro Date
  • Patent number: D827590
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: September 4, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yukimasa Hayashida, Shinichi Iura, Hitoshi Uemura, Daisuke Oya, Kenji Hatori, Yasuhiro Sakai, Ryo Tsuda, Ryutaro Date