Patents by Inventor Ryoichi Hori
Ryoichi Hori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8336528Abstract: An EGR device includes a first cooling passage that introduces a flowing medium discharged from an engine into a main radiator so that the flowing medium is cooled therein, and then returns the flowing medium to the engine, and a second cooling passage that introduces a part of the flowing medium cooled in the first cooling passage to a sub-radiator so that the flowing medium is further cooled therein. The second cooling passage introduces the flowing medium to an EGR cooler to return the flowing medium, which is discharged from the EGR cooler, to the engine.Type: GrantFiled: June 28, 2007Date of Patent: December 25, 2012Assignee: Calsonic Kansei CorporationInventors: Ryoichi Hori, Satoshi Kimura, Satoshi Tamagawa
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Patent number: 8151753Abstract: In a warm-up system that pre-warms up of an engine (E) by transferring heat from a heat source to an engine cooling water circulation circuit (1) of a vehicle, a residential hot water circuit (2) that uses a household heat source is provided as the heat source, and a one-touch connector (3) is provided in the engine cooling water circulation circuit (1) and the residential hot water circuit (2). The one-touch connector (3) connects the two circuits (1, 2) prior to start-up of the engine (E) such that heat is transferred to the engine cooling water circulation circuit (1), and disconnects the two circuits (1, 2) following heat transfer in preparation for start-up of the engine (E).Type: GrantFiled: September 15, 2008Date of Patent: April 10, 2012Assignee: Calsonic Kansei CorporationInventors: Naohisa Kamiyama, Shiro Nakajima, Satoshi Tamagawa, Ryoichi Hori
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Patent number: 8069911Abstract: A radiator including a core part having a plurality of tubes and fins, a tank fluidically connected with the tank, an oil cooler contained in the tank, the oil cooler being provided with a pair of connecting pipes which fluidically communicate an interior of the oil cooler and penetrate a wall portion of the tank. The wall portion is formed with a projecting reinforcement portion which projects therefrom and is formed at least between the connecting pipes.Type: GrantFiled: April 5, 2007Date of Patent: December 6, 2011Assignee: Calsonic Kansei CorporationInventors: Ryoichi Hori, Hiroyuki Okura, Shiro Nakajima
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Publication number: 20100001535Abstract: An exhaust gas thermal energy recovery system of a hybrid electric vehicle includes a second catalytic converter 6, a cooling device 10, a resonance tube 8, control valves V1 and V2 and an electric generating device 9. After an engine 1 is stopped, the control valves V1 and V2 form a loop path 20, and the cooling device 10 cools down an exhaust gas downstream side of the second catalytic converter 6 so as to generate a temperature gradient.Type: ApplicationFiled: August 8, 2007Publication date: January 7, 2010Applicant: CALSONIC KANSEI CORPORATIONInventors: Satoshi Kimura, Ryoichi Hori, Shiro Nakajima, Norimitsu Matsudaira
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Publication number: 20090314266Abstract: An EGR device includes a first cooling passage that introduces a flowing medium discharged from an engine 2 into a main radiator 7 so that the flowing medium is cooled therein, and then returns the flowing medium to the engine 2, and a second cooling passage that introduces a part of the flowing medium cooled in the first cooling passage to a sub-radiator 8 so that the flowing medium is further cooled therein. The second cooling passage introduces the flowing medium to an EGR cooler 6 to return the flowing medium, which is discharged from the EGR cooler 6, to the engine 2.Type: ApplicationFiled: June 28, 2007Publication date: December 24, 2009Inventors: Ryoichi Hori, Satoshi Kimura, Satoshi Tamagawa
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Publication number: 20090241863Abstract: An engine rapid warm-up system includes cooling water circulating through an engine 1, a radiator 2 introducing the cooling water to be cooled, a heat accumulator 3 storing the cooling water heated by the engine 1, and a pipe 6 and a water pump 7 that circulate the cooling water through the engine 1, the radiator 2 and the heat accumulator 3. In the system, high temperature cooling water that is stored in the heat accumulator 3 is controlled to be sent to and warm up the engine 1 at engine start, heat of exhaust gas is controlled to recover so that the cooling water obtained after heat recovery is circulated through and warms up the engine 1.Type: ApplicationFiled: August 2, 2007Publication date: October 1, 2009Inventors: Satoshi Kimura, Ryoichi Hori, Shiro Nakajima, Norimitsu Matsudaira
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Publication number: 20090071428Abstract: In a warm-up system that pre-warms up of an engine (E) by transferring heat from a heat source to an engine cooling water circulation circuit (1) of a vehicle, a residential hot water circuit (2) that uses a household heat source is provided as the heat source, and a one-touch connector (3) is provided in the engine cooling water circulation circuit (1) and the residential hot water circuit (2). The one-touch connector (3) connects the two circuits (1, 2) prior to start-up of the engine (E) such that heat is transferred to the engine cooling water circulation circuit (1), and disconnects the two circuits (1, 2) following heat transfer in preparation for start-up of the engine (E).Type: ApplicationFiled: September 15, 2008Publication date: March 19, 2009Inventors: Naohisa Kamiyama, Shiro Nakajima, Satoshi Tamagawa, Ryoichi Hori
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Patent number: 7499340Abstract: A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.Type: GrantFiled: January 9, 2008Date of Patent: March 3, 2009Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
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Patent number: 7478669Abstract: A plurality of tubes and corrugated fins are piled up and arranged alternatively, for integrally assembled heat exchangers. The corrugated fin has fin portions for the heat exchangers and a connecting portion connecting the fin portions. The connecting portion is formed with slits arranged in first and second lines extending in a longitudinal direction of the fin and at least one louver between the slits in the lines. The slits in the first line and the slits in the second line traverse a top portion and a bottom portion adjacent to the top portion of the fin and the louver is formed on an intermediate portion between the top portion and the bottom portion so that the louver is located between the space of the slits in the first line and the space of the slits in the second line.Type: GrantFiled: April 13, 2006Date of Patent: January 20, 2009Assignee: Calsonic Kansei CorporationInventors: Hiroyuki Okura, Ryoichi Hori, Shinobu Asakawa, Mitsuru Arahori
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Publication number: 20080205111Abstract: A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.Type: ApplicationFiled: January 9, 2008Publication date: August 28, 2008Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
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Patent number: 7345929Abstract: A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.Type: GrantFiled: March 7, 2007Date of Patent: March 18, 2008Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
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Publication number: 20070246201Abstract: A radiator including a core part having a plurality of tubes and fins, a tank fluidically connected with the tank, an oil cooler contained in the tank, the oil cooler being provided with a pair of connecting pipes which fluidically communicate an interior of the oil cooler and penetrate a wall portion of the tank. The wall portion is formed with a projecting reinforcement portion which projects therefrom and is formed at least between the connecting pipes.Type: ApplicationFiled: April 5, 2007Publication date: October 25, 2007Inventors: Ryoichi Hori, Hiroyuki Okura, Shiro Nakajima
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Publication number: 20070242535Abstract: A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.Type: ApplicationFiled: March 7, 2007Publication date: October 18, 2007Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
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Patent number: 7203101Abstract: A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.Type: GrantFiled: January 12, 2006Date of Patent: April 10, 2007Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
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Publication number: 20070051488Abstract: A heat exchanger for a motor vehicle includes a pair of tanks apart from each other, and a core part including a plurality of tubes and a plurality of fins. Each of the fins is arranged between the adjacent tubes, and the tubes are fixed at both end portions thereof with the tanks so that circulating medium can be cooled by air flow running through the core part and flows through the tubes and tanks. Connecting portions of the tubes and the tanks are covered by a windbreak member so that the connecting portions are prevented from being hit by the air flow running through the core port.Type: ApplicationFiled: August 18, 2006Publication date: March 8, 2007Inventor: Ryoichi Hori
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Publication number: 20060237173Abstract: A plurality of tubes and corrugated fins are piled up and arranged alternatively, for integrally assembled heat exchangers. The corrugated fin has fin portions for the heat exchangers and a connecting portion connecting the fin portions. The connecting portion is formed with slits arranged in first and second lines extending in a longitudinal direction of the fin and at least one louver between the slits in the lines. The slits in the first line and the slits in the second line traverse a top portion and a bottom portion adjacent to the top portion of the fin and the louver is formed on an intermediate portion between the top portion and the bottom portion so that the louver is located between the space of the slits in the first line and the space of the slits in the second line.Type: ApplicationFiled: April 13, 2006Publication date: October 26, 2006Inventors: Hiroyuki Okura, Ryoichi Hori, Shinobu Asakawa, Mitsuru Arahori
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Publication number: 20060120125Abstract: A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.Type: ApplicationFiled: January 12, 2006Publication date: June 8, 2006Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
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Patent number: 7016236Abstract: A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.Type: GrantFiled: April 8, 2005Date of Patent: March 21, 2006Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
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Patent number: 7002856Abstract: A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit provided on the semiconductor chip for transforming an external power supply voltage received from the power supply terminal for supplying a source voltage resulting from the voltage transformation to the internal circuit, and a control circuit provided on the semiconductor chip for controlling the power supply circuit, wherein the control circuit includes external power supply voltage detecting means and/or temperature detecting means and responds to the signal from the external power supply voltage detecting means and/or the temperature detecting means by changing the power supply voltage to the internal circuit to thereby maintain the operating speed of the internal circuit to be constant.Type: GrantFiled: May 20, 2005Date of Patent: February 21, 2006Assignee: Renesas Technology CorporationInventors: Takao Watanabe, Ryoichi Hori, Goro Kitsukawa, Yoshiki Kawajiri, Takayuki Kawahara, Kiyoo Itoh
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Patent number: D842288Type: GrantFiled: August 9, 2016Date of Patent: March 5, 2019Assignee: Kabushiki Kaisha UnwindInventors: Ryoichi Hori, Kyoko Uemura