Abstract: A semiconductor device is provided wherein a current mirror circuit controlled by a pulse input voltage is utilized and a load is driven in such a manner that the output current of the current mirror circuit becomes a substantially constant current. Further, the output voltage of the current mirror circuit can be compared with a predetermined reference voltage by a comparator, with the current mirror circuit being controlled by the output voltage of the comparator in accordance with the result of comparison. The driver circuit can be used for driving the data lines of a dynamic random access memory or an external capacitance load. With these techniques, power consumption and peak current are reduced.

Abstract: A semiconductor memory comprises a plurality of first data lines, a plurality of word lines disposed in such a manner as to intersect the first data lines, dynamic memory cells respectively disposed at the intersections between the word lines and the first data lines and including MOS transistors, a second data line connected to the first data lines through a switching circuit, an amplifier circuit connected to the second data line for detecting a read signal, and a write circuit for applying a write signal. The amplifier circuit includes at least one bipolar transistor.

Abstract: The invention relates to a semiconductor device which has a high density of integration and of which a low power consumption is required. The semiconductor device prevents the influence of the amplitude of an input signal upon the amplitude of an output signal in such a way that a preceding circuit and a succeeding circuit are provided with different reference voltages. The semiconductor device is constructed of a circuit which includes a bipolar transistor and an insulated-gate field effect transistor, and which operates with reference to one or more voltages, at least one of the reference voltages having a voltage value different from a reference operating voltage of a preceding circuit.

Abstract: A semiconductor memory having a structure wherein each of data lines intersecting word lines is divided into a plurality of sub lines in its lengthwise direction, memory cells are arranged at the points of intersection between the divided sub lines and the word lines, common input/output lines are disposed in common to a plurality of such sub lines, the common input/output lines and the plurality of sub lines are respectively connected by switching elements, and the switching elements are connected to a decoder through control lines and are selectively driven by control signals generated from the decorder.

Abstract: It is contemplated to realize a semiconductor memory with a large memory capacity, high in integration and low in power dissipation. A semiconductor memory is disclosed, comprising a plurality of blocks each having a memory cell array and sense amplifier(s) to differentially amplify signals read out from the array, wherein a common driving line of amplifiers composed of N-channel MOS transistors among said sense amplifiers and a common driving line of amplifiers composed of P-channel MOS transistors among the sense amplifers are connected between different blocks.

Abstract: A semiconductor memory having a structure wherein each of data lines intersecting word lines is divided into a plurality of sub lines in its lengthwise direction, memory cells are arranged at the points of intersection between the divided sub lines and the word lines, common input/output lines are disposed in common to a plurality of such sub lines, the common input/output lines and the plurality of sub lines are respectively connected by switching elements, and the switching elements are connected to a decoder through control lines and are selectively driven by control signals generated from the decoder.

Abstract: A semiconductor memory is provided which includes a plurality of data lines, a plurality of word lines which are arranged so as to intersect the plurality of data lines, and a plurality of memory cells which are respectively disposed at intersection points between the plurality of data lines and the plurality of word lines. A row decoder selects at least one from among the plurality of word lines, while a column decoder generates a signal for connecting one of the plurality of data lines to an input/output line. A plurality of wiring leads are also provided which are formed of a conductor layer different from conductor layers constituting the plurality of data lines and the plurality of word lines and which are arranged so as to intersect the plurality of data lines.

Abstract: The invention relates to a semiconductor device which has a high density of integration and of which a low power consumption is required. The semiconductor device prevents the influence of the amplitude of an input signal upon the amplitude of an output signal in such a way that a preceding circuit and a succeeding circuit are provided with different reference voltages. The semiconductor device is constructed of a circuit which includes a bipolar transistor and an insulated-gate field effect transistor, and which operates with reference to one or more voltages, at least one of the reference voltages having a voltage value different from a reference operating voltage of a preceding circuit.

Abstract: In order to drive a capacitance load at a high speed without an undesirably large increase in the circuit size, a driving arrangement is provided to charge the capacitance load in accordance with a limited voltage. A voltage limiter is coupled to a supply voltage providing a predetermined limited voltage. A pulse generator is coupled to receive the limited voltage and to provide output pulses which are, in turn, limited in accordance with the output voltage of the voltage limiter. A driver is coupled between the supply voltage and the capacitance load, and is controlled by the output pulses of the pulse generator. In this way, the capacitance load is charged through the driver in accordance with the limited voltage. Since the voltage limiter is not arranged along a series connection between the driver and the capacitance load, the internal equivalent resistance of the voltage limiter does not detrimentally influence the resistance along the series connection.

Abstract: This invention relates to a semiconductor device formed on a semiconductor chip which is provided with at least a voltage transformation arrangement for transforming an external power supply voltage into an internal power supply voltage. At least a portion of circuits formed in the chip operate by using the internal power supply voltage rather than the external power supply voltage. Semiconductor devices, in particular DRAMs (dynamic random access memories), in which said internal power supply voltage is supplied are controlled so that the starting time of the internal power supply voltage at the moment of the switch-on of the external power supply is later than the starting time of the external power supply voltage, and/or the time necessary for the internal power supply voltage to increase to a predetermined operational level at said moment is longer than that required for said external power supply voltage to increase to a predetermined operational level.

Abstract: In a monolithic storage device having bit lines to which a plurality of memory cells are connected, and I/O lines which connect an external data input/output terminal and the bit lines and which exchange data between the input/output terminal and the bit lines; the improvement wherein said bit lines are divided into a plurality of groups each having the I/O lines, and a deserializer circuit is disposed between said each I/O line and an input terminal.

Abstract: A semiconductor memory having a structure wherein each of data lines intersecting word lines is divided into a plurality of sub lines in its lengthwise direction, memory cells are arranged at the points of intersection between the divided sub lines and the word lines, common input/output lines are disposed in common to a plurality of such sub lines, the common input/output lines and the plurality of sub lines are respectively connected by switching elements, and the switching elements are connected to a decoder through control lines and are selectively driven by control signals generated from the decoder.

Abstract: In a semiconductor memory device including memory and dummy cells connected to groups of data lines, word lines and dummy word lines for selecting the memory and dummy cells, respectively, and a signal detector for differentially amplifying the read signal from the memory cell selected by the signal of the word line and a reference signal from the dummy cell, the improvement wherein the memory cell capacitor consists of two capacitors, each having substantially the same structure as a dummy cell capacitor and connected in parallel with the other.

Abstract: In a monolithic storage device having bit lines to which a plurality of memory cells are connected, and I/O lines which connect an external data input/output terminal and the bit lines and which exchange data between the input/output terminal and the bit lines; the improvement wherein said bit lines are divided into a plurality of groups each having the I/O lines, and a deserializer circuit is disposed between said each I/O line and an input terminal.

Abstract: A semiconductor memory is disclosed having data lines divided lengthwise, which data lines cross word lines in a memory cell array and are selectively coupled to memory cells. A plurality of second data lines are arranged, one for each of predetermined groups of the data lines, to exchange data through first switches. Also one or more third data lines are arranged orthogonally to the second data lines to exchange data with the second data lines through second switches. Read/write controllers are coupled to the third data lines. Data is read and written for desired memory cells by selective drive of the word lines and the first and second switches.

Abstract: A dynamic type semiconductor memory using MOS transistors, in which first and second booster circuits utilizing capacitances, respectively, are provided at each of stages preceding and succeeding to a word driver, respectively. Data lines of the memory are each provided with a voltage compensating circuit for increasing a voltage for charging a memory cell to a level higher than a source voltage for being rewritten in the memory cell. A first boosting circuit is operated after a word line driving pulse signal is produced. Subsequently, word driver selecting transistors are turned off, which is followed by operation of the second booster circuit. Thus, the word line voltage is boosted twice.

Abstract: In order to permit reduced component size without reduction of an external power supply voltage, a semiconductor integrated circuit includes at least three circuits. The first of these three circuits converts the external power source voltage to an internal power source voltage which is smaller than the external power voltage. A second circuit is supplied with the external power source voltage and is responsive to first signals which regulate an operation of the integrated circuit. This second circuit generates second signals which control the integrated circuit so that the integrated circuit performs the desired regulated operation. To carry this out, the second circuit includes at least first transistors which are supplied with the external power source voltage and responsive to the first signals. The second signals generated by the second circuit have amplitudes smaller than those of the first signals.

Abstract: A semiconductor memory of multiplexed address inputs is made operative to receive column addresses and row addresses through common external address lines and to decode them consecutively in response to first and second strobe signals thereby to select one of memory cells. The semiconductor memory is equipped with address buffers exclusively for column and row addressing operations, respectively, the outputs of which are consecutively transmitted to column decoders and row decoders through common internal address lines.

Abstract: A first semiconductor circuit element including a first electrode is formed on a semiconductor substrate, an inter-layer insulating layer for insulating the first electrode is formed on the first electrode, and a first penetrating opening is provided in a part of the inter-layer insulating layer.Subsequently, a step of forming a second semiconductor circuit element is carried out, this step including a step of forming a second electrode so that at least a part thereof may overlie the inter-layer insulating layer at an area other than the first penetrating opening. Further, a subsidiary interconnection conductive layer is buried into the first opening. Another insulating layer is formed on the structure thus formed, whereupon second and third penetrating openings are respectively provided in the insulating layer over the second electrode and the interconnection subsidiary conductive layer.First and second interconnection conductors are respectively buried into the second and third penetrating openings.

Abstract: A first semiconductor circuit element including a first electrode is formed on a semiconductor substrate, an insulating layer for insulating the first electrode is formed on the first electrode, and a first opening is provided in a part of this insulating layer.Subsequently, a second semiconductor circuit element is formed by forming a second electrode overlaying in part the insulating layer at an area other than the first opening and, a subsidiary conductive layer is formed in the first opening. Another insulating layer is formed on the structure thus formed, whereupon second and third openings are respectively provided in this latter insulating layer.First and second conductors are respectively deposited in the second and third openings, whereby electrical contact to the first and second electrodes are provided, with contact to the first electrode being via the subsidiary conductive layer.