Patents by Inventor Ryuichi Fujimoto

Ryuichi Fujimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11966210
    Abstract: A substrate processing apparatus includes a device management controller including a parts management control part configured to monitor the state of parts constituting the apparatus, a device state monitoring control part configured to monitor integrity of device data obtained from an operation state of the parts constituting the apparatus, and a data matching control part configured to monitor facility data provided from a factory facility to the apparatus. The device management controller is configured to derive information evaluating the operation state of the apparatus based on a plurality of monitoring result data selected from a group consisting of maintenance timing monitoring result data acquired by the parts management control part, device state monitoring result data acquired by the device state monitoring control part, and utility monitoring result data acquired by the data matching control part.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: April 23, 2024
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Kazuhide Asai, Kazuyoshi Yamamoto, Hidemoto Hayashihara, Takayuki Kawagishi, Kayoko Yashiki, Yukio Miyata, Hiroyuki Iwakura, Masanori Okuno, Kenichi Fujimoto, Ryuichi Kaji
  • Publication number: 20240053497
    Abstract: A radiation imaging apparatus includes a pixel array having a plurality of pixels configured to detect radiation, and a controller configured to obtain a radiation generation condition related to a radiation generating apparatus during fluoroscopic imaging, and determine, during the fluoroscopic imaging, timings of a plurality of sampling and holding operations in each of the plurality of pixels in accordance with the radiation generation condition. The timing of at least one sampling and holding operation is a timing in an irradiation period of radiation, and each of the plurality of pixels includes a conversion element configured to convert radiation into an electrical signal, and a sample and hold circuit configured to sample and hold signals from the conversion element multiple times in accordance with the timings, determined by the controller, of the plurality of sampling and holding operations.
    Type: Application
    Filed: August 4, 2023
    Publication date: February 15, 2024
    Inventors: TAKASHI TAKASAKI, ATSUSHI IWASHITA, KOSUKE TERUI, RYUICHI FUJIMOTO, TAKESHI NODA
  • Publication number: 20230404506
    Abstract: A radiation imaging apparatus includes: a processing unit configured to obtain a plurality of images corresponding to a plurality of different radiation energies by irradiating an object with radiation and performing imaging using an energy spectrum obtained by totaling energy information obtained by dividing a time-serially obtained radiation photon energy in a time direction, and perform energy subtraction processing using the plurality of images.
    Type: Application
    Filed: June 6, 2023
    Publication date: December 21, 2023
    Inventors: Kosuke TERUI, Atsushi IWASHITA, Ryuichi FUJIMOTO
  • Publication number: 20230404505
    Abstract: An information processing apparatus obtains a plurality of results by performing energy subtraction processing for each of a plurality of sets which are sets each formed from a plurality of radiation images corresponding to different radiation energies and in which combinations of radiation energies are different, and determines a value of a predetermined parameter used in the energy subtraction processing such that a dispersion between the plurality of results is reduced.
    Type: Application
    Filed: April 18, 2023
    Publication date: December 21, 2023
    Inventors: Ryuichi FUJIMOTO, Atsushi IWASHITA, Kosuke TERUI
  • Publication number: 20230401677
    Abstract: An image processing apparatus includes: a processing unit configured to perform noise reduction processing and material decomposition processing using a plurality of images corresponding to a plurality of different radiation energies obtained by irradiating an object with radiation and performing imaging. The processing unit generates a noise reduction image by applying filter processing for each frequency component obtained by resolving a thickness image of a material obtained by the material decomposition processing into a plurality of frequencies, and generates an image by material re-decomposition processing using the thickness image after noise reduction, which is obtained by combining the noise reduction images for each frequency component and an accumulation image obtained based on combining of the plurality of images.
    Type: Application
    Filed: April 25, 2023
    Publication date: December 14, 2023
    Inventors: Atsushi IWASHITA, Kosuke TERUI, Ryuichi FUJIMOTO
  • Publication number: 20230360185
    Abstract: An image processing apparatus includes: a generation unit configured to generate a first image representing a thickness of a first material and a second image representing a thickness of a second material different from the first material using a plurality of images obtained based on a first combination of different radiation energies, and to generate a third image representing the thickness of the first material and a fourth image representing the thickness of the second material using a plurality of images obtained based on a second combination of different radiation energies; and an obtaining unit configured to obtain, using one of the first image and the second image and one of the third image and the fourth image, an enhanced image in which a third material different from the first material and the second material is enhanced.
    Type: Application
    Filed: July 13, 2023
    Publication date: November 9, 2023
    Inventors: Kosuke TERUI, Atsushi IWASHITA, Ryuichi FUJIMOTO
  • Publication number: 20230263492
    Abstract: An image processing apparatus is provided that includes: an obtaining unit configured to obtain a plurality of images relating to different radiation energies; and a generating unit configured to generate at least one of energy-subtraction images based on the plurality of images using a learned model, wherein the learned model is obtained using a first image obtained using a radiation and a second image obtained by improving image-quality of the first image or by adding a noise which has been artificially calculated to the first image.
    Type: Application
    Filed: February 14, 2023
    Publication date: August 24, 2023
    Inventors: Manabu YAMAZOE, Atsushi IWASHITA, Ryuichi FUJIMOTO, Osamu SAGANO, Ritsuya TOMITA
  • Publication number: 20230153970
    Abstract: An image processing apparatus comprises a processing unit configured to performing energy subtraction processing using information concerning a plurality of attenuation rates corresponding to a plurality of radiation energies that are different from each other and are obtained by performing imaging in which an object is irradiated with radiation. The processing unit estimates attenuation information of a decomposition target material contained in the object using at least one image obtained by the energy subtraction processing, and generates an image concerning the decomposition target material using the attenuation information and the information concerning the plurality of attenuation rates.
    Type: Application
    Filed: January 19, 2023
    Publication date: May 18, 2023
    Inventors: Atsushi IWASHITA, Kosuke TERUI, Ryuichi FUJIMOTO
  • Publication number: 20220366543
    Abstract: An image processing apparatus performs first noise reduction processing on a plurality of radiation images corresponding to mutually-different radiation energies, generates a decomposition image by energy subtraction processing using the plurality of radiation images obtained by performing the first noise reduction processing, and performs second noise reduction processing on the decomposition image, wherein the second noise reduction processing uses a filter that differs from a filter used in the first noise reduction processing in at least one of size and type.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 17, 2022
    Inventors: Atsushi Iwashita, Kosuke Terui, Ryuichi Fujimoto, Sota Torii
  • Publication number: 20220302817
    Abstract: A power supply circuit has a first node, a second node, a DC-DC converter that includes a switched capacitor, generates an output voltage based on an input voltage supplied from the first node, and outputs the output voltage from the second node, and a regulator that is connected in parallel to the DC-DC converter between the first node and the second node and controls an output current flowing to the second node based on a reference voltage lower than the input voltage.
    Type: Application
    Filed: September 15, 2021
    Publication date: September 22, 2022
    Inventors: Makoto MORIMOTO, Rui ITO, Ryuichi FUJIMOTO
  • Publication number: 20220091050
    Abstract: An image processing apparatus generates a plurality of attenuation rate images using a plurality of radiation images corresponding to a plurality of different radiation energies obtained by irradiating an object with radiation, corrects the radiation images or the attenuation rate images so as to reduce an error of an attenuation rate caused depending on at least one of a dose of the radiation, a thickness of the object, and energy of the radiation, and generates a material characteristic image by energy subtraction processing using the plurality of attenuation rate images after the correction.
    Type: Application
    Filed: December 2, 2021
    Publication date: March 24, 2022
    Inventors: Atsushi IWASHITA, Sota TORII, Takeshi NODA, Kosuke TERUI, Akira TSUKUDA, Ryuichi FUJIMOTO
  • Patent number: 11100975
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of memory cells connected to a word line, a circuit configured to apply a voltage to the word line, a detection circuit configured to detect a first time difference from when a first signal of which a voltage is increased with a first slope is applied to the word line to when a current flows through the memory cells in response to applying the first signal, and a second time difference from when a second signal of which a voltage is increased with a second slope is applied to the word line to when a current flows through the memory cells in response to applying the second signal, the second slope being different from the first slope, and a determination circuit configured to determine a threshold voltage of the memory cells based on a difference between the first time difference and the second time difference.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: August 24, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Rui Ito, Makoto Morimoto, Yutaka Shimizu, Ryuichi Fujimoto
  • Publication number: 20210090633
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of memory cells connected to a word line, a circuit configured to apply a voltage to the word line, a detection circuit configured to detect a first time difference from when a first signal of which a voltage is increased with a first slope is applied to the word line to when a current flows through the memory cells in response to applying the first signal, and a second time difference from when a second signal of which a voltage is increased with a second slope is applied to the word line to when a current flows through the memory cells in response to applying the second signal, the second slope being different from the first slope, and a determination circuit configured to determine a threshold voltage of the memory cells based on a difference between the first time difference and the second time difference.
    Type: Application
    Filed: February 27, 2020
    Publication date: March 25, 2021
    Applicant: KIOXIA CORPORATION
    Inventors: Rui ITO, Makoto MORIMOTO, Yutaka SHIMIZU, Ryuichi FUJIMOTO
  • Patent number: 10593405
    Abstract: According to one embodiment, a semiconductor memory device includes: a word line; a first memory cell; a first circuit; and a second circuit. The first memory cell is connected to the word line. The first circuit generates a first voltage having a waveform including a first time period during which a voltage value increases with time and a second time period during which the voltage value decreases with time, and applies the generated first voltage to the word line. The second circuit measures first time from a first timing when a state of the first memory cell changes according to the first voltage to a second timing when the state of the first memory cell changes according to the first voltage after the first timing. The second circuit determines first data stored in the first memory cell on the basis of the measured first time.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: March 17, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Ryuichi Fujimoto, Kan Shimizu, Shigehito Saigusa, Motoki Nagata, Yumi Takada, Hitoshi Shiga, Makoto Morimoto
  • Publication number: 20190295649
    Abstract: According to one embodiment, a semiconductor memory device includes: a word line; a first memory cell; a first circuit; and a second circuit. The first memory cell is connected to the word line. The first circuit generates a first voltage having a waveform including a first time period during which a voltage value increases with time and a second time period during which the voltage value decreases with time, and applies the generated first voltage to the word line. The second circuit measures first time from a first timing when a state of the first memory cell changes according to the first voltage to a second timing when the state of the first memory cell changes according to the first voltage after the first timing. The second circuit determines first data stored in the first memory cell on the basis of the measured first time.
    Type: Application
    Filed: August 13, 2018
    Publication date: September 26, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Ryuichi FUJIMOTO, Kan SHIMIZU, Shigehito SAIGUSA, Motoki NAGATA, Yumi TAKADA, Hitoshi SHIGA, Makoto MORIMOTO
  • Publication number: 20150063175
    Abstract: According to an embodiment, a wireless communication apparatus includes a clock transmitting unit, a function circuit and a control unit. The clock transmitting unit is configured to transmit a clock signal through one of a plurality of transmission paths. The transmission paths are different from each other. The function circuit is configured to operate in synchronization with the clock signal transmitted by the clock transmitting unit. The control unit is configured to select one of the plurality of transmission paths according to an operation state of the wireless communication apparatus.
    Type: Application
    Filed: February 14, 2014
    Publication date: March 5, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Yoshihara, Ryuichi Fujimoto
  • Patent number: 8948307
    Abstract: According to one embodiment, an ASK signal generator includes a differential oscillator, a first modulator, a second modulator, a first transmission line, a second transmission line and an impedance adjustment circuit. The differential oscillator generates first and second signals having an opposite phase, and outputs the first and second signals from first and second output terminals. The first modulator connected to the first output terminal is set in the normally off state. The second modulator connected to the second output terminal is turned on or off according to a digital signal. The first and second transmission lines connected to the first and second output terminals have a length equal to a ¼ wavelength of the oscillation frequency of the differential oscillator. The impedance adjustment circuit is operated together with the second modulator according to the digital signal.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: February 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryuichi Fujimoto
  • Publication number: 20130251067
    Abstract: According to one embodiment, an ASK signal generator includes a differential oscillator, a first modulator, a second modulator, a first transmission line, a second transmission line and an impedance adjustment circuit. The differential oscillator generates first and second signals having an opposite phase, and outputs the first and second signals from first and second output terminals. The first modulator connected to the first output terminal is set in the normally off state. The second modulator connected to the second output terminal is turned on or off according to a digital signal. The first and second transmission lines connected to the first and second output terminals have a length equal to a ¼ wavelength of the oscillation frequency of the differential oscillator. The impedance adjustment circuit is operated together with the second modulator according to the digital signal.
    Type: Application
    Filed: February 28, 2013
    Publication date: September 26, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Ryuichi FUJIMOTO
  • Patent number: 8008973
    Abstract: A transistor is provided to amplify a high frequency signal. A gate/base of the transistor receives the high frequency input signal. A variable capacitor is connected between the gate and a source/between the base and an emitter of the transistor. A variable inductor is connected with the source/the emitter of the transistor.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: August 30, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryuichi Fujimoto
  • Publication number: 20110068871
    Abstract: A transistor is provided to amplify a high frequency signal. A gate/base of the transistor receives the high frequency input signal. A variable capacitor is connected between the gate and a source/between the base and an emitter of the transistor. A variable inductor is connected with the source/the emitter of the transistor.
    Type: Application
    Filed: March 8, 2010
    Publication date: March 24, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Ryuichi Fujimoto