Abstract: A method for forming fin structures is provided. Sacrificial structures are provided on a substrate. Fin structures are formed on the sides of the sacrificial structures. The forming of the fin structures comprises a plurality of cycles, wherein each cycle comprises a fin deposition phase and a fin profile shaping phase. The sacrificial structure is removed.

Abstract: A feature in a layer is provided. A photoresist layer is formed over the layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls, where the photoresist features have a first critical dimension. A conformal layer is deposited over the sidewalls of the photoresist features to reduce the critical dimensions of the photoresist features. Features are etched into the layer, wherein the layer features have a second critical dimension, which is less than the first critical dimension.

Abstract: A method for forming features in an etch layer is provided. A first mask is formed over the etch layer where the first mask defines a plurality of spaces with widths. The first mask is laterally etched where the etched first mask defines a plurality of spaces with widths that are greater than the widths of the spaces of the first mask. A sidewall layer is formed over the etched first mask where the sidewall layer defines a plurality of spaces with widths that are less than the widths of the spaces defined by the etched first mask. Features are etched into the etch layer through the sidewall layer, where the features have widths that are smaller than the widths of the spaces defined by the etched first mask. The mask and sidewall layer are removed.

Abstract: A method for reducing capacitances between semiconductor device wirings is provided. A sacrificial layer is formed over a dielectric layer. A plurality of features are etched into the sacrificial layer and dielectric layer. The features are filled with a filler material. The sacrificial layer is removed, so that parts of the filler material remain exposed above a surface of the dielectric layer, where spaces are between the exposed parts of the filler material, where the spaces are in an area formerly occupied by the sacrificial layer. Widths of the spaces between the parts of the filler material are shrunk with a shrink sidewall deposition. Gaps are etched into the dielectric layer through the shrink sidewall deposition. The filler material and shrink sidewall deposition are removed.

Abstract: A process for plasma etching silicon carbide with selectivity to an overlying and/or underlying dielectric layer of material. The dielectric material can comprise silicon dioxide, silicon oxynitride, silicon nitride or various low-k dielectric materials including organic low-k materials. The etching gas includes a chlorine containing gas such as Cl2, an oxygen containing gas such as O2, and a carrier gas such as Ar. In order to achieve a desired selectivity to such dielectric materials, the plasma etch gas chemistry is selected to achieve a desired etch rate of the silicon carbide while etching the dielectric material at a slower rate. The process can be used to selectively etch a hydrogenated silicon carbide etch stop layer or silicon carbide substrate.

Abstract: A method for forming a feature in an etch layer is provided. A photoresist layer is formed over the etch layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A control layer is formed over the photoresist layer and bottoms of the photoresist features. A conformal layer is deposited over the sidewalls of the photoresist features and control layer to reduce the critical dimensions of the photoresist features. Openings in the control layer are opened with a control layer breakthrough chemistry. Features are etched into the etch layer with an etch chemistry, which is different from the control layer break through chemistry, wherein the control layer is more etch resistant to the etch with the etch chemistry than the conformal layer.

Abstract: A method for forming dual damascene features in a dielectric layer. Vias are partially etched in the dielectric layer. A trench pattern mask is formed over the dielectric layer. Trenches are partially etched in the dielectric layer. The trench pattern mask is stripped. The dielectric layer is further etched to complete etch the vias and the trenches in the dielectric layer.

Abstract: A method for processing substrate to form a semiconductor device is disclosed. The substrate includes an etch stop layer disposed above a metal layer. The method includes etching through the etch stop layer down to the copper metal layer, using a plasma etch process that utilizes a chlorine-containing etchant source gas, thereby forming etch stop layer openings in the etch stop layer. The etch stop layer includes at least one of a SiN and SiC material. Thereafter, the method includes performing a wet treatment on the substrate using a solution that contains acetic acid (CH3COOH) or acetic acid/ammonium hydroxide (NH4OH) to remove at least some of the copper oxides. Alternatively, the copper oxides may be removed using a H2 plasma. BTA passivation may be optionally performed on the substrate.

Abstract: A method for etching a feature in a layer is provided. An underlayer of a polymer material is formed over the layer. A top image layer is formed over the underlayer. The top image layer is exposed to patterned radiation. A pattern is developed in the top image layer. The pattern is transferred from the top image layer to the underlayer with a reducing dry etch. The layer is etched through the underlayer, where the top image layer is completely removed and the underlayer is used as a pattern mask during the etching the layer to transfer the pattern from the underlayer to the layer.

Abstract: A method for creating semiconductor devices by etching a layer over a wafer is provided. A photoresist layer is provided on a wafer. The photoresist layer is patterned. The wafer is placed in a process chamber. The photoresist is hardened by providing a hardening plasma containing high energy electrons in the process chamber to harden the photoresist layer, wherein the high energy electrons have a density. The layer is etched within the process chamber with an etching plasma, where a density of high energy electrons in the etching plasma is less than the density of high energy electrons in the hardening plasma.

Abstract: A method of approximating an ion energy distribution function (IEDF) at a substrate surface of a substrate, the substrate being processed in a plasma processing chamber. There is included providing a first voltage value, the first voltage value representing a value of a first voltage that represents a DC potential (VDC) at the substrate surface. There is also included providing a peak low frequency RF voltage value (VLFRF(PEAK)) during plasma processing, the peak low frequency RF voltage (VLFRF(PEAK)) value representing a peak value of a low frequency RF voltage (VLFRF) supplied to the plasma processing chamber.

Abstract: The invention relates to the etching of a dielectric layer in an integrated circuit (IC) structure having a patterned metal hard mask layer. The method comprises feeding a gas mixture that includes a carbon monoxide (CO) and at least one fluorocarbon gas mixture into a reactor. The gas mixture has no oxygen (O2) gas. The gas mixture is then converted into a plasma. The plasma selectively etches the dielectric layer. Typically, the dielectric layer comprises silicon.

Abstract: A semiconductor manufacturing process wherein silicon nitride is plasma etched with selectivity to an overlying and/or underlying dielectric layer such as a silicon oxide or low-k material. The etchant gas includes a fluorocarbon reactant and an oxygen reactant, the ratio of the flow rate of the oxygen reactant to that of the fluorocarbon reactant being no greater than 1.5. The etch rate of the silicon nitride can be at least 5 times higher than that of the oxide. Using a combination of CH3F and O2 with optional carrier gasses such as Ar and/or N2, it is possible to obtain nitride:oxide etch rate selectivities of over 40:1. The process is useful for simultaneously removing silicon nitride in 0.25 micron and smaller contact or via openings and wide trenches in forming structures such as damascene and self-aligned structures.

Abstract: A system and method for achieving a silicon carbide to low-k dielectric etch selectivity ratio of greater than 1:1 using a chlorine containing gas and either hydrogen (H2) gas or nitrogen (N2) gas is described. The method is applied to a semiconductor substrate having a low-k dielectric layer and a silicon carbide layer. The chlorine containing gas is a gas mixture that includes either HCl, BCl3, Cl2, or any combination thereof. In one embodiment, the method provides for supplying an etchant gas comprising a chlorine containing gas and a hydrogen (H2) gas. The etchant gas is then energized to generate a plasma which then etches openings in the silicon carbide at a faster etch rate than the low-k dielectric etch rate. In an alternative embodiment, the etchant gas mixture comprises a chlorine containing gas and a nitrogen (N2) gas.

Abstract: The present inventions is a method of trench formation within a dielectric layer, comprising, first, etching a via within the dielectric layer. After the via is etched, an organic plug is used to fill a portion of the via. After the desired amount of organic plug has been etched from the via, a trench is etched with a first gas mixture to a first depth, and a second gas mixture is used to further etch the trench to the final desired trench depth. Preferably, the method is used for low-k dielectrics that do not have an intermediate etch stop layer. Additionally, it is preferable that the first gas mixture is a polymeric gas mixture and the second gas mixture is a non-polymeric gas mixture. As a result of using this method, an interconnect structure for a low-k dielectric without an intermediate etch stop layer having a trench with trench edges that are substantially orthogonal and a via with via edges that are substantially orthogonal is generated.

Abstract: A method of forming a damascene structure above a substrate is provided. A low-k dielectric layer is formed over the substrate, wherein the low-k dielectric layer does not have a trench stop layer. A plurality of vias are etched through the low-k dielectric layer. Via plugs are formed in the plurality of vias. A plurality of trenches are etched into the low-k dielectric layer, wherein the etching with sufficiently high via plugs minimizes facet formation at the tops of vias exposed to the etch and wherein the trench etch process removes fences caused by the via plugs. The via plugs are stripped.

Abstract: A method for etching a feature in a layer is provided. An underlayer of a polymer material is formed over the layer. A top image layer is formed over the underlayer. The top image layer is exposed to patterned radiation. A pattern is developed in the top image layer. The pattern is transferred from the top image layer to the underlayer with a reducing dry etch. The layer is etched through the underlayer, where the top image layer is completely removed and the underlayer is used as a pattern mask during the etching the layer to transfer the pattern from the underlayer to the layer.

Abstract: The present inventions is a method of trench formation within a dielectric layer, comprising, first, etching a via within the dielectric layer. After the via is etched, an organic plug is used to fill a portion of the via. After the desired amount of organic plug has been etched from the via, a trench is etched with a first gas mixture to a first depth, and a second gas mixture is used to further etch the trench to the final desired trench depth. Preferably, the method is used for low-k dielectrics that do not have an intermediate etch stop layer. Additionally, it is preferable that the first gas mixture is a polymeric gas mixture and the second gas mixture is a non-polymeric gas mixture. As a result of using this method, an interconnect structure for a low-k dielectric without an intermediate etch stop layer having a trench with trench edges that are substantially orthogonal and a via with via edges that are substantially orthogonal is generated.

Abstract: The present inventions is a method of trench formation within a dielectric layer, comprising, first, etching a via within the dielectric layer. After the via is etched, an organic plug is used to fill a portion of the via. After the desired amount of organic plug has been etched from the via, a trench is etched with a first gas mixture to a first depth, and a second gas mixture is used to further etch the trench to the final desired trench depth. Preferably, the method is used for low-k dielectrics that do not have an intermediate etch stop layer. Additionally, it is preferable that the first gas mixture is a polymeric gas mixture and the second gas mixture is a non-polymeric gas mixture. As a result of using this method, an interconnect structure for a low-k dielectric without an intermediate etch stop layer having a trench with trench edges that are substantially orthogonal and a via with via edges that are substantially orthogonal is generated.

Abstract: The invention provides a process for plasma etching silicon carbide with selectivity to an overlapping and/or underlying dielectric layer of material. The etching gas includes a hydrogen-containing fluorocarbon gas such as CH3F, an oxygen-containing gas such as O2 and an optional carrier gas such as Ar. The dielectric material can comprise silicon dioxide, silicon nitride, silicon oxynitride or various low-k dielectric materials including organic low-k materials. In order to achieve a desired selectivity to such dielectric materials, the plasma etch gas chemistry is selected to achieve a desired etch rate of the silicon carbide while etching the dielectric material at a slower rate. The process can be used to selectively etch a hydrogenated silicon carbide etch stop layer or silicon carbide substrates.