Patents by Inventor Sae Hee Hwang

Sae Hee Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240188293
    Abstract: A semiconductor memory device including a substrate; a mold structure including gate electrodes and mold insulating layers stacked in a stair shape, channel structures on the substrate, intersecting the gate electrodes, and passing through the mold structure; cell contacts connected to the gate electrodes; a first interlayer insulating layer on the mold structure and covering the channel structures and cell contacts; first metal patterns connected to the channel structures, an upper surface of the first metal patterns being coplanar with an upper surface of the first interlayer insulating layer; second metal patterns connected to the cell contacts, an upper surface of the second metal patterns being coplanar with the upper surface of the first metal patterns; a first blocking layer along the upper surface of the first interlayer insulating layer, the first metal patterns, and the second metal patterns; and a first dummy vias passing through the first blocking layer.
    Type: Application
    Filed: August 2, 2023
    Publication date: June 6, 2024
    Inventors: Sam Ki KIM, Nam Bin KIM, Ji Woong KIM, Tae Hun KIM, Ki Bong MOON, Sae Rom LEE, Sung-Bok LEE, Jun Hee LIM, Nag Yong CHOI, Sun Gyung HWANG
  • Publication number: 20240188294
    Abstract: A semiconductor memory device comprising a substrate including a cell array area and an extension area, a mold structure including, a plurality of gate electrodes sequentially stacked on the cell array area of the substrate and stacked in a stair shape on the extension area of the substrate, and a plurality of mold insulating films stacked alternately with the plurality of gate electrodes, a plurality of channel structures on the cell array area of the substrate, wherein each of the plurality of channel structures extends through the mold structure and intersects the plurality of gate electrodes, a plurality of cell contacts on the extension area of the substrate and respectively connected to the plurality of gate electrodes, a first interlayer insulating film on the mold structure so as to cover the plurality of channel structures and the plurality of cell contacts.
    Type: Application
    Filed: August 11, 2023
    Publication date: June 6, 2024
    Inventors: Sam Ki KIM, Nam Bin KIM, Ji Woong KIM, Tae Hun KIM, Sae Rom LEE, Jun Hee LIM, Nag Yong CHOI, Sun Gyung HWANG
  • Publication number: 20220295975
    Abstract: Proposed is a brush for applying makeup. The brush according to the present disclosure includes: a large brush (100); a receiving space (140) formed along a length direction of the large brush (100) at a position corresponding to or eccentric from a center of the large brush (100) so that the receiving space (140) is open at upper and lower ends thereof and at a side of a circumference thereof; and a small brush (200) configured to be coupled to the large brush (100) in a direction from top to bottom of the receiving space (140) so as to coincide with a disposition direction of the large brush (100) so that the small brush (200) is used in conjunction with the large brush (100) as one integrated brush (300), or separated from the large brush (100) in a direction from bottom to top thereof and selectively used.
    Type: Application
    Filed: March 16, 2021
    Publication date: September 22, 2022
    Inventor: Sae-Hee HWANG
  • Patent number: D814805
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: April 10, 2018
    Assignee: BAOSHENG CORPORATION
    Inventor: Sae Hee Hwang
  • Patent number: D866192
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: November 12, 2019
    Assignee: Baosheng Corporation
    Inventor: Sae Hee Hwang