Patents by Inventor Sagar Borikar

Sagar Borikar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230388244
    Abstract: Techniques for sending Compute Express Link (CXL) packets over Ethernet (CXL-E) in a composable data center that may include disaggregated, composable servers. The techniques may include receiving, from a first server device, a request to bind the first server device with a multiple logical device (MLD) appliance. Based at least in part on the request, a first CXL-E connection may be established for the first server device to export a computing resource to the MLD appliance. The techniques may also include receiving, from the MLD appliance, an indication that the computing resource is available, and receiving, from a second server device, a second request for the computing resource. Based at least in part on the second request, a second CXL-E connection may be established for the second server device to consume or otherwise utilize the computing resource of the first server device via the MLD appliance.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Chakradhar Kar, Sagar Borikar, Ramesh Sivakolundu, Ayan Banerjee, Anant Thakar
  • Publication number: 20230385223
    Abstract: A Compute Express Link™ (CXL) over Ethernet (COE) station is provided to bridge a CXL fabric and an Ethernet network to allow for efficient native memory load/store access to remotely connected resources. The COE station supports CXL and Ethernet traffic through its CXL interface, scheduler/packers, decoders, VOQs and VIQs by adding COE tags to Ethernet frames. In CXL controller mode, the CXL controller drives the VOQs. In Ethernet mode, the COE module drives the VOQs, and interacts with the MAC sublayer and the PMA sublayer, which are responsible for encoding and decoding data signals for transmission through a serializer/deserializer.
    Type: Application
    Filed: June 6, 2023
    Publication date: November 30, 2023
    Applicant: Elastics.cloud, Inc.
    Inventors: Shreyas Shah, Jeffrey S. Earl, Anant Thakar, Sagar Borikar
  • Patent number: 11824793
    Abstract: Techniques for sending Compute Express Link (CXL) packets over Ethernet (CXL-E) in a composable data center that may include disaggregated, composable servers. The techniques may include receiving, from a first server device, a request to bind the first server device with a multiple logical device (MLD) appliance. Based at least in part on the request, a first CXL-E connection may be established for the first server device to export a computing resource to the MLD appliance. The techniques may also include receiving, from the MLD appliance, an indication that the computing resource is available, and receiving, from a second server device, a second request for the computing resource. Based at least in part on the second request, a second CXL-E connection may be established for the second server device to consume or otherwise utilize the computing resource of the first server device via the MLD appliance.
    Type: Grant
    Filed: February 8, 2023
    Date of Patent: November 21, 2023
    Assignee: Cisco Technology, Inc.
    Inventors: Chakradhar Kar, Sagar Borikar, Ramesh Sivakolundu, Ayan Banerjee, Anant Thakar
  • Publication number: 20230224255
    Abstract: Techniques for sending Compute Express Link (CXL) packets over Ethernet (CXL-E) in a composable data center that may include disaggregated, composable servers. The techniques may include receiving, from a first server device, a request to bind the first server device with a multiple logical device (MLD) appliance. Based at least in part on the request, a first CXL-E connection may be established for the first server device to export a computing resource to the MLD appliance. The techniques may also include receiving, from the MLD appliance, an indication that the computing resource is available, and receiving, from a second server device, a second request for the computing resource. Based at least in part on the second request, a second CXL-E connection may be established for the second server device to consume or otherwise utilize the computing resource of the first server device via the MLD appliance.
    Type: Application
    Filed: March 15, 2023
    Publication date: July 13, 2023
    Inventors: Ayan Banerjee, Ramesh Sivakolundu, Chakradhar Kar, Sagar Borikar, Anant Thakar
  • Publication number: 20230188474
    Abstract: Techniques for sending Compute Express Link (CXL) packets over Ethernet (CXL-E) in a composable data center that may include disaggregated, composable servers. The techniques may include receiving, from a first server device, a request to bind the first server device with a multiple logical device (MLD) appliance. Based at least in part on the request, a first CXL-E connection may be established for the first server device to export a computing resource to the MLD appliance. The techniques may also include receiving, from the MLD appliance, an indication that the computing resource is available, and receiving, from a second server device, a second request for the computing resource. Based at least in part on the second request, a second CXL-E connection may be established for the second server device to consume or otherwise utilize the computing resource of the first server device via the MLD appliance.
    Type: Application
    Filed: February 8, 2023
    Publication date: June 15, 2023
    Inventors: Chakradhar Kar, Sagar Borikar, Ramesh Sivakolundu, Ayan Banerjee, Anant Thakar
  • Patent number: 11632337
    Abstract: Techniques for sending Compute Express Link (CXL) packets over Ethernet (CXL-E) in a composable data center that may include disaggregated, composable servers. The techniques may include receiving, from a first server device, a request to bind the first server device with a multiple logical device (MLD) appliance. Based at least in part on the request, a first CXL-E connection may be established for the first server device to export a computing resource to the MLD appliance. The techniques may also include receiving, from the MLD appliance, an indication that the computing resource is available, and receiving, from a second server device, a second request for the computing resource. Based at least in part on the second request, a second CXL-E connection may be established for the second server device to consume or otherwise utilize the computing resource of the first server device via the MLD appliance.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: April 18, 2023
    Assignee: Cisco Technology, Inc.
    Inventors: Ayan Banerjee, Ramesh Sivakolundu, Chakradhar Kar, Sagar Borikar, Anant Thakar
  • Publication number: 20230116820
    Abstract: Techniques for sending Compute Express Link (CXL) packets over Ethernet (CXL-E) in a composable data center that may include disaggregated, composable servers. The techniques may include receiving, from a first server device, a request to bind the first server device with a multiple logical device (MLD) appliance. Based at least in part on the request, a first CXL-E connection may be established for the first server device to export a computing resource to the MLD appliance. The techniques may also include receiving, from the MLD appliance, an indication that the computing resource is available, and receiving, from a second server device, a second request for the computing resource. Based at least in part on the second request, a second CXL-E connection may be established for the second server device to consume or otherwise utilize the computing resource of the first server device via the MLD appliance.
    Type: Application
    Filed: May 23, 2022
    Publication date: April 13, 2023
    Inventors: Ayan Banerjee, Ramesh Sivakolundu, Chakradhar Kar, Sagar Borikar, Anant Thakar
  • Patent number: 11625335
    Abstract: Systems and methods provide for optimizing utilization of an Address Translation Cache (ATC). A network interface controller (NIC) can write information reserving one or more cache lines in a first level of the ATC to a second level of the ATC. The NIC can receive a request for a direct memory access (DMA) to an untranslated address in memory of a host computing system. The NIC can determine that the untranslated address is not cached in the first level of the ATC. The NIC can identify a selected cache line in the first level of the ATC to evict using the request and the second level of the ATC. The NIC can receive a translated address for the untranslated address. The NIC can cache the untranslated address in the selected cache line. The NIC can perform the DMA using the translated address.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: April 11, 2023
    Assignee: Cisco Technology, Inc.
    Inventors: Sagar Borikar, Ravikiran Kaidala Lakshman
  • Patent number: 11601377
    Abstract: Techniques for sending Compute Express Link (CXL) packets over Ethernet (CXL-E) in a composable data center that may include disaggregated, composable servers. The techniques may include receiving, from a first server device, a request to bind the first server device with a multiple logical device (MLD) appliance. Based at least in part on the request, a first CXL-E connection may be established for the first server device to export a computing resource to the MLD appliance. The techniques may also include receiving, from the MLD appliance, an indication that the computing resource is available, and receiving, from a second server device, a second request for the computing resource. Based at least in part on the second request, a second CXL-E connection may be established for the second server device to consume or otherwise utilize the computing resource of the first server device via the MLD appliance.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: March 7, 2023
    Assignee: Cisco Technology, Inc.
    Inventors: Chakradhar Kar, Sagar Borikar, Ramesh Sivakolundu, Ayan Banerjee, Anant Thakar
  • Patent number: 11336581
    Abstract: A method is provided by which a network adapter device receives a packet sent over a network from a peer, the packet including an enqueue timestamp indicating when the packet has been enqueued at the network adapter device. The network adapter device parses a header of the packet to detect whether the header includes bits indicating that the peer device is experiencing congestion, and obtains packet metadata of the packet and the enqueue timestamp of the packet. The network adapter device compares the packet metadata with information in a flow table to identify an entry in the flow table corresponding to a flow to which the packet metadata matches. The network adapter device sets a timer associated with the flow, the timer for use in scheduling transmission of a next packet provided by the host to be sent to the peer.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: May 17, 2022
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Sagar Borikar, John William Marshall
  • Patent number: 11080225
    Abstract: In one example, at least one peripheral interconnect switch obtains, from a first endpoint device, a message initiating a direct memory access data transfer between the first endpoint device and a second endpoint device. The message indicates an address assigned to the second endpoint device by a host device as a destination of the message. Based on the address assigned to the second endpoint device by the host device, the at least one peripheral interconnect switch identifies an address assigned to the second endpoint device by the at least one peripheral interconnect switch. In response to identifying the address assigned to the second endpoint device by the at least one peripheral interconnect switch, the at least one peripheral interconnect switch provides the message to the second endpoint device.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: August 3, 2021
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Sagar Borikar, Anant Thakar
  • Publication number: 20210182212
    Abstract: Systems and methods provide for optimizing utilization of an Address Translation Cache (ATC). A network interface controller (NIC) can write information reserving one or more cache lines in a first level of the ATC to a second level of the ATC. The NIC can receive a request for a direct memory access (DMA) to an untranslated address in memory of a host computing system. The NIC can determine that the untranslated address is not cached in the first level of the ATC. The NIC can identify a selected cache line in the first level of the ATC to evict using the request and the second level of the ATC. The NIC can receive a translated address for the untranslated address. The NIC can cache the untranslated address in the selected cache line. The NIC can perform the DMA using the translated address.
    Type: Application
    Filed: February 8, 2021
    Publication date: June 17, 2021
    Inventors: Sagar Borikar, Ravikiran Kaidala Lakshman
  • Patent number: 11036649
    Abstract: Presented herein are techniques enable existing hardware input/output resources, such as the hardware queues (queue control registers), of a network interface card to be shared with different hosts (i.e., each queue mapped to many hosts) by logically segregating the hardware I/O resources using assignable interfaces each associated with a distinct Process Address Space Identifier (PASID). That is, different assignable interfaces are created and associated with different PASIDs, and these assignable interfaces each correspond to a different host (i.e., there is a mapping between a host, an assignable interface, a PASID, and a partition of a hardware queue). The result is that that the hosts can use the assignable interface to directly access the hardware queue partition that corresponds thereto.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: June 15, 2021
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Ravikiran Kaidala Lakshman, Tanjore K. Suresh, Deepak Srinivas Mayya, Sagar Borikar
  • Patent number: 10949370
    Abstract: An example method for facilitating policy-driven storage in a microserver computing environment is provided and includes receiving, at an input/output (I/O) adapter in a microserver chassis having a plurality of compute nodes and a shared storage resource, policy contexts prescribing storage access parameters of respective compute nodes and enforcing the respective policy contexts on I/O operations by the compute nodes, in which respect a particular I/O operation by any compute node is not executed if the respective policy context does not allow the particular I/O operation. The method further includes allocating tokens to command descriptors associated with I/O operations for accessing the shared storage resource, identifying a violation of any policy context of any compute node based on availability of the tokens, and throttling I/O operations by other compute nodes until the violation disappears.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: March 16, 2021
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Prabhath Sajeepa, Sagar Borikar
  • Patent number: 10929310
    Abstract: Systems and methods provide for optimizing utilization of an Address Translation Cache (ATC). A network interface controller (NIC) can write information reserving one or more cache lines in a first level of the ATC to a second level of the ATC. The NIC can receive a request for a direct memory access (DMA) to an untranslated address in memory of a host computing system. The NIC can determine that the untranslated address is not cached in the first level of the ATC. The NIC can identify a selected cache line in the first level of the ATC to evict using the request and the second level of the ATC. The NIC can receive a translated address for the untranslated address. The NIC can cache the untranslated address in the selected cache line. The NIC can perform the DMA using the translated address.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: February 23, 2021
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Sagar Borikar, Ravikiran Kaidala Lakshman
  • Patent number: 10908841
    Abstract: Presented herein are methodologies for increasing effective throughput on a network. A method includes receiving a command request via a communication bus, the command request including a command ID, determining, based on the command ID, whether data in the command request is to be joined with data from other command requests having the same command ID, when it is determined, based on the command ID, that the data in the command request is to be joined with other data from other command requests having the same command ID, writing the data to a selected buffer in which the other data is already stored, and causing the data and the other data in the buffer to be sent as a payload of a single packet across a communications fabric.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: February 2, 2021
    Assignee: Cisco Technology, Inc.
    Inventors: Ravikiran Kaidala Lakshman, Deepak Srinivas Mayya, Tanjore K. Suresh, David S. Walker, Sagar Borikar, Shrikant Vaidya
  • Patent number: 10872056
    Abstract: An example method for facilitating remote memory access with memory mapped addressing among multiple compute nodes is executed at an input/output (IO) adapter in communication with the compute nodes over a Peripheral Component Interconnect Express (PCIE) bus, the method including: receiving a memory request from a first compute node to permit access by a second compute node to a local memory region of the first compute node; generating a remap window region in a memory element of the IO adapter, the remap window region corresponding to a base address register (BAR) of the second compute node; and configuring the remap window region to point to the local memory region of the first compute node, wherein access by the second compute node to the BAR corresponding with the remap window region results in direct access of the local memory region of the first compute node by the second compute node.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: December 22, 2020
    Assignee: CISCO TECHNOLOGY, INC.
    Inventor: Sagar Borikar
  • Publication number: 20200320017
    Abstract: Presented herein are techniques enable existing hardware input/output resources, such as the hardware queues (queue control registers), of a network interface card to be shared with different hosts (i.e., each queue mapped to many hosts) by logically segregating the hardware I/O resources using assignable interfaces each associated with a distinct Process Address Space Identifier (PASID). That is, different assignable interfaces are created and associated with different PASIDs, and these assignable interfaces each correspond to a different host (i.e., there is a mapping between a host, an assignable interface, a PASID, and a partition of a hardware queue). The result is that that the hosts can use the assignable interface to directly access the hardware queue partition that corresponds thereto.
    Type: Application
    Filed: April 4, 2019
    Publication date: October 8, 2020
    Inventors: Ravikiran Kaidala Lakshman, Tanjore K. Suresh, Deepak Srinivas Mayya, Sagar Borikar
  • Publication number: 20200301873
    Abstract: In one example, at least one peripheral interconnect switch obtains, from a first endpoint device, a message initiating a direct memory access data transfer between the first endpoint device and a second endpoint device. The message indicates an address assigned to the second endpoint device by a host device as a destination of the message. Based on the address assigned to the second endpoint device by the host device, the at least one peripheral interconnect switch identifies an address assigned to the second endpoint device by the at least one peripheral interconnect switch. In response to identifying the address assigned to the second endpoint device by the at least one peripheral interconnect switch, the at least one peripheral interconnect switch provides the message to the second endpoint device.
    Type: Application
    Filed: March 18, 2019
    Publication date: September 24, 2020
    Inventors: Sagar Borikar, Anant Thakar
  • Patent number: 10785161
    Abstract: A method is provided by which a network adapter device receives a packet sent over a network from a peer, the packet including an enqueue timestamp indicating when the packet has been enqueued at the network adapter device. The network adapter device parses a header of the packet to detect whether the header includes bits indicating that the peer device is experiencing congestion, and obtains packet metadata of the packet and the enqueue timestamp of the packet. The network adapter device compares the packet metadata with information in a flow table to identify an entry in the flow table corresponding to a flow to which the packet metadata matches. The network adapter device sets a timer associated with the flow, the timer for use in scheduling transmission of a next packet provided by the host to be sent to the peer.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: September 22, 2020
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Sagar Borikar, John William Marshall