Patents by Inventor Sagar Borikar
Sagar Borikar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200296049Abstract: A method is provided by which a network adapter device receives a packet sent over a network from a peer, the packet including an enqueue timestamp indicating when the packet has been enqueued at the network adapter device. The network adapter device parses a header of the packet to detect whether the header includes bits indicating that the peer device is experiencing congestion, and obtains packet metadata of the packet and the enqueue timestamp of the packet. The network adapter device compares the packet metadata with information in a flow table to identify an entry in the flow table corresponding to a flow to which the packet metadata matches. The network adapter device sets a timer associated with the flow, the timer for use in scheduling transmission of a next packet provided by the host to be sent to the peer.Type: ApplicationFiled: May 29, 2020Publication date: September 17, 2020Inventors: Sagar Borikar, John William Marshall
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Publication number: 20200278935Abstract: Systems and methods provide for optimizing utilization of an Address Translation Cache (ATC). A network interface controller (NIC) can write information reserving one or more cache lines in a first level of the ATC to a second level of the ATC. The NIC can receive a request for a direct memory access (DMA) to an untranslated address in memory of a host computing system. The NIC can determine that the untranslated address is not cached in the first level of the ATC. The NIC can identify a selected cache line in the first level of the ATC to evict using the request and the second level of the ATC. The NIC can receive a translated address for the untranslated address. The NIC can cache the untranslated address in the selected cache line. The NIC can perform the DMA using the translated address.Type: ApplicationFiled: March 1, 2019Publication date: September 3, 2020Inventors: Sagar Borikar, Ravikiran Kaidala Lakshman
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Publication number: 20200201799Abstract: An example method for facilitating policy-driven storage in a microserver computing environment is provided and includes receiving, at an input/output (I/O) adapter in a microserver chassis having a plurality of compute nodes and a shared storage resource, policy contexts prescribing storage access parameters of respective compute nodes and enforcing the respective policy contexts on I/O operations by the compute nodes, in which respect a particular I/O operation by any compute node is not executed if the respective policy context does not allow the particular I/O operation. The method further includes allocating tokens to command descriptors associated with I/O operations for accessing the shared storage resource, identifying a violation of any policy context of any compute node based on availability of the tokens, and throttling I/O operations by other compute nodes until the violation disappears.Type: ApplicationFiled: February 28, 2020Publication date: June 25, 2020Inventors: Prabhath Sajeepa, Sagar Borikar
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Publication number: 20200097212Abstract: Presented herein are methodologies for increasing effective throughput on a network. A method includes receiving a command request via a communication bus, the command request including a command ID, determining, based on the command ID, whether data in the command request is to be joined with data from other command requests having the same command ID, when it is determined, based on the command ID, that the data in the command request is to be joined with other data from other command requests having the same command ID, writing the data to a selected buffer in which the other data is already stored, and causing the data and the other data in the buffer to be sent as a payload of a single packet across a communications fabric.Type: ApplicationFiled: September 24, 2018Publication date: March 26, 2020Inventors: Ravikiran Kaidala Lakshman, Deepak Srinivas Mayya, Tanjore K. Suresh, David S. Walker, Sagar Borikar, Shrikant Vaidya
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Patent number: 10585830Abstract: An example method for facilitating policy-driven storage in a microserver computing environment is provided and includes receiving, at an input/output (I/O) adapter in a microserver chassis having a plurality of compute nodes and a shared storage resource, policy contexts prescribing storage access parameters of respective compute nodes and enforcing the respective policy contexts on I/O operations by the compute nodes, in which respect a particular I/O operation by any compute node is not executed if the respective policy context does not allow the particular I/O operation. The method further includes allocating tokens to command descriptors associated with I/O operations for accessing the shared storage resource, identifying a violation of any policy context of any compute node based on availability of the tokens, and throttling I/O operations by other compute nodes until the violation disappears.Type: GrantFiled: January 12, 2018Date of Patent: March 10, 2020Assignee: CISCO TECHNOLOGY, INC.Inventors: Prabhath Sajeepa, Sagar Borikar
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Publication number: 20200021532Abstract: A method is provided by which a network adapter device receives a packet sent over a network from a peer, the packet including an enqueue timestamp indicating when the packet has been enqueued at the network adapter device. The network adapter device parses a header of the packet to detect whether the header includes bits indicating that the peer device is experiencing congestion, and obtains packet metadata of the packet and the enqueue timestamp of the packet. The network adapter device compares the packet metadata with information in a flow table to identify an entry in the flow table corresponding to a flow to which the packet metadata matches. The network adapter device sets a timer associated with the flow, the timer for use in scheduling transmission of a next packet provided by the host to be sent to the peer.Type: ApplicationFiled: July 10, 2018Publication date: January 16, 2020Inventors: Sagar Borikar, John William Marshall
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Publication number: 20190370216Abstract: An example method for facilitating remote memory access with memory mapped addressing among multiple compute nodes is executed at an input/output (IO) adapter in communication with the compute nodes over a Peripheral Component Interconnect Express (PCIE) bus, the method including: receiving a memory request from a first compute node to permit access by a second compute node to a local memory region of the first compute node; generating a remap window region in a memory element of the IO adapter, the remap window region corresponding to a base address register (BAR) of the second compute node; and configuring the remap window region to point to the local memory region of the first compute node, wherein access by the second compute node to the BAR corresponding with the remap window region results in direct access of the local memory region of the first compute node by the second compute node.Type: ApplicationFiled: August 16, 2019Publication date: December 5, 2019Inventor: Sagar Borikar
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Patent number: 10333865Abstract: An example method for transformation of Peripheral Component Interconnect Express (PCIe) compliant virtual devices in a server in a network environment is provided and includes receiving, during runtime of the server, a request to change a first configuration of a PCIe compliant virtual device to a different second configuration, identifying a bridge on a PCIe topology below which the virtual device is located, issuing a simulated secondary bus reset to the bridge, the virtual device being reconfigured according to the change in configuration after the simulated secondary bus reset is issued, re-enumerating below the bridge after the change in configuration completes without rebooting the server, and updating the PCI topology with the virtual device in the second configuration. A virtual interface card adapter traps the simulated secondary bus reset, removes the virtual device from the PCI topology, and reconfigures the virtual device from the first configuration to the second configuration.Type: GrantFiled: August 21, 2015Date of Patent: June 25, 2019Assignee: CISCO TECHNOLOGY, INC.Inventors: Sagar Borikar, Prabhath Sajeepa
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Publication number: 20180335971Abstract: Presented herein are techniques for virtualizing functions of a Non-Volatile Memory Express (NVMe) controller that manages access to non-volatile memory such as a solid state drive. An example method includes receiving, at a Peripheral Component Interconnect Express (PCIe) interface card that is in communication with a PCIe bus, configuration information for virtual interfaces that support a non-volatile memory express interface protocol, wherein the virtual interfaces virtualize a NVMe controller, configuring the virtual interfaces in accordance with the configuration information, presenting the virtual interfaces to the PCIe bus, and receiving, by at least one of the virtual interfaces, from a host in communication with the at least one of the virtual interfaces via the PCIe bus, a message for a queue of the at least one of the virtual interfaces that is mapped to a queue of the non-volatile memory express controller.Type: ApplicationFiled: May 16, 2017Publication date: November 22, 2018Inventor: Sagar Borikar
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Patent number: 10114792Abstract: An example method for facilitating low latency remote direct memory access (RDMA) for microservers is provided and includes generating queue pair (QPs) in a memory of an input/output (I/O) adapter of a microserver chassis having a plurality of compute nodes executing thereon, the QPs being associated with a remote direct memory access (RDMA) connection between a first compute node and a second compute node in the microserver chassis, setting a flag in the QPs to indicate that the RDMA connection is local to the microserver chassis, and performing a loopback of RDMA packets within the I/O adapter from one memory region in the I/O adapter associated with the first compute node of the RDMA connection to another memory region in the I/O adapter associated with the second compute node of the RDMA connection.Type: GrantFiled: September 14, 2015Date of Patent: October 30, 2018Assignee: CISCO TECHNOLOGY, INCInventors: Prabhath Sajeepa, Sagar Borikar
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Patent number: 10114764Abstract: An example method for facilitating multi-level paging and address translation in a network environment is provided and includes receiving a request for memory in a physical memory of a network element, associating the request with a first virtual address space, mapping a memory region located in the physical memory to a first window in the first virtual address space, the memory region being also mapped to a second window in a different, second virtual address space, remapping the first window in the first virtual address space to the second window in the second virtual address space, and responding to the request with addresses of the second window in the second virtual address space.Type: GrantFiled: March 2, 2018Date of Patent: October 30, 2018Assignee: CISCO TECHNOLOGY, INCInventor: Sagar Borikar
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Patent number: 10089267Abstract: A method is provided in one example embodiment and includes receiving by a network element a request from a network device connected to the network element to update a shared resource maintained by the network element; subsequent to the receipt, identifying a Base Address Register Resource Table (“BRT”) element assigned to a Peripheral Component Interconnect (“PCI”) adapter of the network element associated with the network device, wherein the BRT points to the shared resource; changing an attribute of the identified BRT from read-only to read/write to enable the identified BRT to be written by the network device; and notifying the network device that the attribute of the identified BRT has been changed, thereby enabling the network device to update the shared resource via a Base Address Register (“BAR”) comprising the identified BRT.Type: GrantFiled: September 8, 2017Date of Patent: October 2, 2018Assignee: CISCO TECHNOLOGY, INC.Inventors: Sagar Borikar, Prabhath Sajeepa
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Publication number: 20180189191Abstract: An example method for facilitating multi-level paging and address translation in a network environment is provided and includes receiving a request for memory in a physical memory of a network element, associating the request with a first virtual address space, mapping a memory region located in the physical memory to a first window in the first virtual address space, the memory region being also mapped to a second window in a different, second virtual address space, remapping the first window in the first virtual address space to the second window in the second virtual address space, and responding to the request with addresses of the second window in the second virtual address space.Type: ApplicationFiled: March 2, 2018Publication date: July 5, 2018Inventor: Sagar Borikar
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Publication number: 20180137073Abstract: An example method for facilitating policy-driven storage in a microserver computing environment is provided and includes receiving, at an input/output (I/O) adapter in a microserver chassis having a plurality of compute nodes and a shared storage resource, policy contexts prescribing storage access parameters of respective compute nodes and enforcing the respective policy contexts on I/O operations by the compute nodes, in which respect a particular I/O operation by any compute node is not executed if the respective policy context does not allow the particular I/O operation. The method further includes allocating tokens to command descriptors associated with I/O operations for accessing the shared storage resource, identifying a violation of any policy context of any compute node based on availability of the tokens, and throttling I/O operations by other compute nodes until the violation disappears.Type: ApplicationFiled: January 12, 2018Publication date: May 17, 2018Inventors: Prabhath Sajeepa, Sagar Borikar
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Patent number: 9965441Abstract: An example method for adaptively coalescing remote direct memory access (RDMA) acknowledgements is provided. The method includes determining one or more input/output (I/O) characteristics of RDMA packets of a plurality of queue pairs (QPs) on a per-QP basis, each QP identifying a respective RDMA connection between a respective first compute node and a respective second compute node. The method further includes determining an acknowledgement frequency for providing acknowledgements of the RDMA packets on a per-QP basis (i.e., a respective acknowledgement frequency is set for each QP) based on the determined one or more I/O characteristics for each QP.Type: GrantFiled: December 10, 2015Date of Patent: May 8, 2018Assignee: CISCO TECHNOLOGY, INC.Inventors: Prabhath Sajeepa, Sagar Borikar
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Patent number: 9921970Abstract: An example method for facilitating multi-level paging and address translation in a network environment is provided and includes receiving a request for memory in a physical memory of a network element, associating the request with a first virtual address space, mapping a memory region located in the physical memory to a first window in the first virtual address space, the memory region being also mapped to a second window in a different, second virtual address space, remapping the first window in the first virtual address space to the second window in the second virtual address space, and responding to the request with addresses of the second window in the second virtual address space.Type: GrantFiled: March 22, 2016Date of Patent: March 20, 2018Assignee: CISCO TECHNOLOGY, INC.Inventor: Sagar Borikar
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Patent number: 9892075Abstract: An example method for facilitating policy-driven storage in a microserver computing environment is provided and includes receiving, at an input/output (I/O) adapter in a microserver chassis having a plurality of compute nodes and a shared storage resource, policy contexts prescribing storage access parameters of respective compute nodes and enforcing the respective policy contexts on I/O operations by the compute nodes, in which respect a particular I/O operation by any compute node is not executed if the respective policy context does not allow the particular I/O operation. The method further includes allocating tokens to command descriptors associated with I/O operations for accessing the shared storage resource, identifying a violation of any policy context of any compute node based on availability of the tokens, and throttling I/O operations by other compute nodes until the violation disappears.Type: GrantFiled: December 10, 2015Date of Patent: February 13, 2018Assignee: CISCO TECHNOLOGY, INC.Inventors: Prabhath Sajeepa, Sagar Borikar
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Publication number: 20180011807Abstract: A method is provided in one example embodiment and includes receiving by a network element a request from a network device connected to the network element to update a shared resource maintained by the network element; subsequent to the receipt, identifying a Base Address Register Resource Table (“BRT”) element assigned to a Peripheral Component Interconnect (“PCI”) adapter of the network element associated with the network device, wherein the BRT points to the shared resource; changing an attribute of the identified BRT from read-only to read/write to enable the identified BRT to be written by the network device; and notifying the network device that the attribute of the identified BRT has been changed, thereby enabling the network device to update the shared resource via a Base Address Register (“BAR”) comprising the identified BRT.Type: ApplicationFiled: September 8, 2017Publication date: January 11, 2018Inventors: Sagar Borikar, Prabhath Sajeepa
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Publication number: 20170351639Abstract: An example method for facilitating remote memory access with memory mapped addressing among multiple compute nodes is executed at an input/output (IO) adapter in communication with the compute nodes over a Peripheral Component Interconnect Express (PCIE) bus, the method including: receiving a memory request from a first compute node to permit access by a second compute node to a local memory region of the first compute node; generating a remap window region in a memory element of the IO adapter, the remap window region corresponding to a base address register (BAR) of the second compute node; and configuring the remap window region to point to the local memory region of the first compute node, wherein access by the second compute node to the BAR corresponding with the remap window region results in direct access of the local memory region of the first compute node by the second compute node.Type: ApplicationFiled: June 6, 2016Publication date: December 7, 2017Applicant: CISCO TECHNOLOGY, INC.Inventor: Sagar Borikar
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Patent number: 9760513Abstract: A method is provided in one example embodiment and includes receiving by a network element a request from a network device connected to the network element to update a shared resource maintained by the network element; subsequent to the receipt, identifying a Base Address Register Resource Table (“BRT”) element assigned to a Peripheral Component Interconnect (“PCI”) adapter of the network element associated with the network device, wherein the BRT points to the shared resource; changing an attribute of the identified BRT from read-only to read/write to enable the identified BRT to be written by the network device; and notifying the network device that the attribute of the identified BRT has been changed, thereby enabling the network device to update the shared resource via a Base Address Register (“BAR”) comprising the identified BRT.Type: GrantFiled: September 22, 2015Date of Patent: September 12, 2017Assignee: CISCO TECHNOLOGY, INC.Inventors: Sagar Borikar, Prabhath Sajeepa