Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes forming a first oxide layer on a surface of a substrate. The first oxide layer is exposed to a first decoupled plasma nitridation process having a first bias. Subsequently, a charge-trapping layer is formed on the first oxide layer. The charge-trapping layer is exposed to an oxidation process and then to a second decoupled plasma nitridation process having a second, different, bias.

Abstract: A blocking layer of a non-volatile charge trap memory device is formed by oxidizing a portion of a charge trapping layer of the memory device. In one embodiment, the blocking layer is grown by a radical oxidation process at temperature below 500° C. In accordance with one implementation, the radical oxidation process involves flowing hydrogen (H2) and oxygen (O2) gas mixture into a process chamber and exposing the substrate to a plasma. In a preferred embodiment, a high density plasma (HDP) chamber is employed to oxidize a portion of the charge trapping layer. In further embodiments, a portion of a silicon-rich silicon oxynitride charge trapping layer is consumptively oxidized to form the blocking layer and provide an increased memory window relative to oxidation of a nitrogen-rich silicon oxynitride layer.

Abstract: Deposition and anneal operations are iterated to break a deposition into a number of sequential deposition-anneal operations to reach a desired annealed dielectric layer thickness. In one particular embodiment, a two step anneal is performed including an NH3 or ND3 ambient followed by an N2O or NO ambient. In one embodiment, such a method is employed to form a dielectric layer having a stoichiometry attainable with only a deposition process but with a uniform material quality uncharacteristically high of a deposition process. In particular embodiments, sequential deposition-anneal operations provide an annealed first dielectric layer upon which a second dielectric layer may be left substantially non-annealed.

Abstract: A semiconductor device including an oxide-nitride-oxide (ONO) structure having a multi-layer charge storing layer and methods of forming the same are provided. Generally, the method involves: (i) forming a first oxide layer of the ONO structure; (ii) forming a multi-layer charge storing layer comprising nitride on a surface of the first oxide layer; and (iii) forming a second oxide layer of the ONO structure on a surface of the multi-layer charge storing layer. Preferably, the charge storing layer comprises at least two silicon oxynitride layers having differing stoichiometric compositions of Oxygen, Nitrogen and/or Silicon. More preferably, the ONO structure is part of a silicon-oxide-nitride-oxide-silicon (SONOS) structure and the semiconductor device is a SONOS memory transistor. Other embodiments are also disclosed.

Abstract: A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region and a pair of source and drain regions. A gate stack is above the substrate over the channel region and between the pair of source and drain regions. The gate stack includes a high dielectric constant blocking region.

Abstract: A method for forming a tunneling layer of a nonvolatile trapped-charge memory device and the article made thereby. The method includes multiple oxidation and nitridation operations to provide a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a tunneling layer having nitrogen at the substrate interface. The method provides for an improved memory window in a SONOS-type device. In one embodiment, the method includes an oxidation, a nitridation, a reoxidation and a renitridation. In one implementation, the first oxidation is performed with O2 and the reoxidation is performed with NO.

Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes providing a substrate having a charge-trapping layer disposed thereon. A portion of the charge-trapping layer is then oxidized to form a blocking dielectric layer above the charge-trapping layer by exposing the charge-trapping layer to a radical oxidation process.

Abstract: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

Abstract: A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region and a pair of source/drain regions. A gate stack is above the substrate over the channel region and between the pair of source/drain regions. The gate stack includes a multi-layer charge-trapping region having a first deuterated layer. The multi-layer charge-trapping region may further include a deuterium-free charge-trapping layer.

Abstract: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

Abstract: Scaling a nonvolatile trapped-charge memory device and the article made thereby. In an embodiment, scaling includes multiple oxidation and nitridation operations to provide a tunneling layer with a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a tunneling layer having nitrogen at the substrate interface. In an embodiment, scaling includes forming a charge trapping layer with a non-homogenous oxynitride stoichiometry. In one embodiment the charge trapping layer includes a silicon-rich, oxygen-rich layer and a silicon-rich, oxygen-lean oxynitride layer on the silicon-rich, oxygen-rich layer. In an embodiment, the method for scaling includes a dilute wet oxidation to density a deposited blocking oxide and to oxidize a portion of the silicon-rich, oxygen-lean oxynitride layer.

Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes first forming a tunnel dielectric layer on a substrate in a first process chamber of a single-wafer cluster tool. A charge-trapping layer is then formed on the tunnel dielectric layer in a second process chamber of the single-wafer cluster tool. A top dielectric layer is then formed on the charge-trapping layer in the second or in a third process chamber of the single-wafer cluster tool.

Abstract: A nonvolatile charge trap memory device and a method to form the same are described. The device includes a channel region having a channel length with <100> crystal plane orientation. The channel region is between a pair of source and drain regions and a gate stack is disposed above the channel region.

Abstract: A method of forming structures comprises depositing silicon nitride films simultaneously on a plurality of substrates at a first temperature, and heating the silicon nitride films at a temperature greater than the first temperature.

Abstract: In one embodiment, a self-aligned contact (SAC) trench structure is formed through a dielectric layer to expose an active region of a MOS transistor. The SAC trench structure not only exposes the active region for electrical connection but also removes portions of a stress liner over the active region. This leaves the stress liner mostly on the sidewall and top of the gate of the MOS transistor. Removing portions of the stress liner over the active region substantially removes the lateral component of the strain imparted by the stress liner on the substrate, allowing for improved drive current without substantially degrading a complementary MOS transistor.

Abstract: A method for depositing a high-k dielectric coating onto a substrate, such as a semiconductor wafer, is provided. The substrate is subjected to one or more reaction cycles. For instance, in a typical reaction cycle, the substrate is heated to a certain deposition temperature. Thereafter, in one embodiment, one or more reactive organo-metallic gas precursors are supplied to the reactor vessel. An oxidizing gas is also supplied to the substrate at a certain oxidizing temperature to oxidize and/or densify the layers. As a result, a metal oxide coating is formed that has a thickness equal to at least about one monolayer, and in some instances, two or more monolayers. The dielectric constant of the resulting metal oxide coating is often greater than about 4, and in some instance, is from about 10 to about 80.

Abstract: A method for depositing a high-k dielectric coating onto a substrate, such as a semiconductor wafer, is provided. The substrate is subjected to one or more reaction cycles. For instance, in a typical reaction cycle, the substrate is heated to a certain deposition temperature. Thereafter, in one embodiment, one or more reactive organo-metallic gas precursors are supplied to the reactor vessel. An oxidizing gas is also supplied to the substrate at a certain oxidizing temperature to oxidize and/or densify the layers. As a result, a metal oxide coating is formed that has a thickness equal to at least about one monolayer, and in some instances, two or more monolayers. The dielectric constant of the resulting metal oxide coating is often greater than about 4, and in some instance, is from about 10 to about 80.

Abstract: A method for depositing a high-k dielectric coating onto a substrate, such as a semiconductor wafer, is provided. In one embodiment, the process is directed to forming a nitride layer on a substrate. In an alternative embodiment, the present invention is directed to forming a metal oxide or silicate on a semiconductor wafer. When forming a metal oxide or silicate, a passivation layer is first deposited onto the substrate.

Abstract: A method for depositing a high-k dielectric coating onto a substrate, such as a semiconductor wafer, is provided. The substrate is subjected to one or more reaction cycles. For instance, in a typical reaction cycle, the substrate is heated to a certain deposition temperature. Thereafter, in one embodiment, one or more reactive organo-metallic gas precursors are supplied to the reactor vessel. An oxidizing gas is also supplied to the substrate at a certain oxidizing temperature to oxidize and/or densify the layers. As a result, a metal oxide coating is formed that has a thickness equal to at least about one monolayer, and in some instances, two or more monolayers. The dielectric constant of the resulting metal oxide coating is often greater than about 4, and in some instance, is from about 10 to about 80.

Abstract: A method for depositing a high-k dielectric coating onto a substrate, such as a semiconductor wafer, is provided. In one embodiment, the process is directed to forming a nitride layer on a substrate. In an alternative embodiment, the present invention is directed to forming a metal oxide or silicate on a semiconductor wafer. When forming a metal oxide or silicate, a passivation layer is first deposited onto the substrate.