Patents by Inventor Sam Seiichiro Ochi

Sam Seiichiro Ochi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6922320
    Abstract: Embodiments of the present invention provide methods and circuitry for protecting a circuit during hot-swap events. Hot swap protection circuitry includes as overcurrent detection circuit which decouples power from a load. Circuitry is provided to detect ground-fault conditions. Noise detection circuitry is provided to reduce noise in the power that is delivered to the load.
    Type: Grant
    Filed: March 8, 2004
    Date of Patent: July 26, 2005
    Assignee: Ixys Corporation
    Inventor: Sam Seiichiro Ochi
  • Patent number: 6917227
    Abstract: A power module includes a power semiconductor device having a first terminal, a second terminal, and a third terminal. The second terminal is a control terminal to regulate flow of electricity between the first and third terminals. A gate driver has an output node coupled to the second terminal of the power device. The gate driver includes an upper transistor and a lower transistor provided in a half-bridge configuration. The output node of the gate driver is provided between the upper and lower transistors. A first delay circuit is coupled to a control terminal of the upper transistor to provide a first delay period for a first gate drive signal being applied to the control terminal of the upper transistor. A second delay circuit is coupled to a control terminal of the lower transistor to provide a second delay period for a second gate drive signal being applied to the control terminal the lower transistor. The first delay period is different from the second delay period.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: July 12, 2005
    Assignee: IXYS Corporation
    Inventor: Sam Seiichiro Ochi
  • Patent number: 6897492
    Abstract: A gate driver includes a control signal generator having a first input and configured to output a gate control signal to a power semiconductor switch. The gate control signal generator is provided proximate a high side of the gate driver. A first sub-circuit has a first signal path and a second signal path that are suitable for transmitting signals. The first and second signal paths are coupled to the first input of the gate control signal generator. The second signal path is configured to provide a signal to the first input with a reduced signal delay. A comparator is configured to receive signals from the high side. The comparator is provided proximate a low side of the gate driver.
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: May 24, 2005
    Assignee: IXYS Corporation
    Inventor: Sam Seiichiro Ochi
  • Patent number: 6832356
    Abstract: A power module includes a power semiconductor device having a first terminal, a second terminal, and a third terminal. The second terminal is a control terminal to regulate flow of electricity between the first and third terminals. A gate driver has an output node coupled to the second terminal of the power device. The gate driver is configured to output a first conductive state, a second conductive state, and a third conductive state. A pull-down resistor has a first end and a second end. The first end of the pull-down resistor is coupled to the output of the gate driver.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: December 14, 2004
    Assignee: Ixys Corporation
    Inventor: Sam Seiichiro Ochi
  • Publication number: 20040233603
    Abstract: Embodiments of the present invention provide methods and circuitry for protecting a circuit during hot-swap events. Hot swap protection circuitry includes as overcurrent detection circuit which decouples power from a load. Circuitry is provided to detect ground-fault conditions. Noise detection circuitry is provided to reduce noise in the power that is delivered to the load.
    Type: Application
    Filed: March 8, 2004
    Publication date: November 25, 2004
    Applicant: Ixys Corporation
    Inventor: Sam Seiichiro Ochi
  • Publication number: 20040155692
    Abstract: A gate driver includes a control signal generator having a first input and configured to output a gate control signal to a power semiconductor switch. The gate control signal generator is provided proximate a high side of the gate driver. A first sub-circuit has a first signal path and a second signal path that are suitable for transmitting signals. The first and second signal paths are coupled to the first input of the gate control signal generator. The second signal path is configured to provide a signal to the first input with a reduced signal delay. A comparator is configured to receive signals from the high side. The comparator is provided proximate a low side of the gate driver.
    Type: Application
    Filed: December 1, 2003
    Publication date: August 12, 2004
    Applicant: IXYS Corporation
    Inventor: Sam Seiichiro Ochi
  • Patent number: 6771478
    Abstract: Embodiments of the present invention provide methods and circuitry for protecting a circuit during hot-swap events. Hot swap protection circuitry includes as overcurrent detection circuit which decouples power from a load. Circuitry is provided to detect ground-fault conditions. Noise detection circuitry is provided to reduce noise in the power that is delivered to the load.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: August 3, 2004
    Assignee: Ixys Corporation
    Inventor: Sam Seiichiro Ochi
  • Patent number: 6759692
    Abstract: A gate driver includes a gate control signal generator having a first input and configured to output a gate control signal to a power semiconductor switch and a first sub-circuit having a first signal path and a second signal path that are suitable for transmitting signals. The first and second signal paths are coupled to the first input of the gate control signal generator. The second signal path is configured to provide a signal to the first input with a reduced signal delay.
    Type: Grant
    Filed: January 22, 2003
    Date of Patent: July 6, 2004
    Assignee: IXYS Corporation
    Inventor: Sam Seiichiro Ochi
  • Patent number: 6638808
    Abstract: A method for forming a gate driver configured to drive a power semiconductor device includes providing a substrate having an upper surface; forming a conductive region on a portion of the upper surface of the substrate; forming a dielectric layer overlying the conductive region; forming a first conductive layer provided over the conductive region and at least a portion of the dielectric layer; patterning the first conductive layer to provide the first conductive layer with a given resistance value; forming a second conductive layer over the dielectric layer and electrically coupled to the conductive region and first conductive layer; and patterning the second conductive layer to provide an input node that is coupled to a first portion of the resistor and an output node that is coupled to a second portion of the resistor. The input node is configured to receive a control signal from a control signal generator and the output node is configured to receive the control signal from the input node via the resistor.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: October 28, 2003
    Assignee: IXYS Corporation
    Inventor: Sam Seiichiro Ochi
  • Publication number: 20020118501
    Abstract: Embodiments of the present invention provide methods and circuitry for protecting a circuit during hot-swap events. Hot swap protection circuitry includes as overcurrent detection circuit which decouples power from a load. Circuitry is provided to detect ground-fault conditions. Noise detection circuitry is provided to reduce noise in the power that is delivered to the load.
    Type: Application
    Filed: December 21, 2001
    Publication date: August 29, 2002
    Applicant: IXYS Corporation
    Inventor: Sam Seiichiro Ochi
  • Patent number: 5731729
    Abstract: An apparatus for suppressing voltage transients across a first transistor is described. The first transistor has a first terminal, a second terminal, and a gate terminal, and is characterized by an avalanche breakdown voltage rating between the first and second terminals. The cathode of a first diode is coupled to the first terminal, the first diode having a reverse breakdown voltage which is less than the avalanche breakdown voltage rating. Gate driver circuitry is provided by which the gate terminal of the first transistor is coupled to the anode of the first diode. The gate driver circuitry provides a drive signal to the gate terminal of the first transistor, and comprises a plurality of bipolar transistors. Each bipolar transistor has an anode terminal (i.e., base terminal), a p-n junction, and a cathode terminal (i.e., emitter terminal). The anode terminal of each bipolar transistor is coupled to the anode of the first diode.
    Type: Grant
    Filed: January 13, 1995
    Date of Patent: March 24, 1998
    Assignee: IXYS Corporation
    Inventor: Sam Seiichiro Ochi
  • Patent number: 5654896
    Abstract: Apparatus (30) and method (70) for predicting the future performance of a semiconductor power module, power device, or high power integrated circuit for the purpose of planning its repair or replacement before it actually fails. The apparatus provides a central processor (33), output device (37), user interface (39), system memory (35), and data base (41). The method is provided by an application specific integrated circuit (45) or custom software program (45). The method provides a measurement and testing procedure for device parameters such as thermal resistance R.sub.thJC, power supply voltage V.sub.DD, and power supply current I.sub.DD. These device parameters typically characterize various chip components including the die attached interface, chip structure, and bonding wires. As these components degrade, the method via monitoring device parameters turns-off the device and its peripheral circuits and apparatus in an orderly manner.
    Type: Grant
    Filed: October 31, 1994
    Date of Patent: August 5, 1997
    Inventor: Sam Seiichiro Ochi