Abstract: A method includes providing pulse width modulated signals. Each pulse width modulated signal is associated with a different bit, and the bits are arranged in an order to indicate an intensity of a pixel cell. Different frequencies are established for at least two of the pulse width modulated signals. Based on the logical states of the bits, the pulse width modulated signals are combined to form another signal, and the pixel cell is driven with this other signal.

Abstract: An embodiment of the present invention provides a signal generator for generating a signal with a predetermined frequency. The signal generator includes a first comparator for generating a first error signal and a second comparator for generating a second error signal. The first and second comparators are coupled to an oscillator configured to receive the first and second error signals and generate the signal having a predetermined frequency. Another embodiment of the present invention provides a signal generator for generating a signal with a predetermined frequency. The signal generator includes a counter for generating a first count, Q_last. The counter is coupled to a ratio counter which generates a signal having a value less than or equal to Q_last. The contents of the ratio counter represent the phase of the signal having a predetermined frequency. The ratio counter outputs the signal having a predetermined frequency.

Abstract: An embodiment of the present invention provides a signal generator for generating a signal with a predetermined frequency. The signal generator includes a first comparator for generating a first error signal and a second comparator for generating a second error signal. The first and second comparators are coupled to an oscillator configured to receive the first and second error signals and generate the signal having a predetermined frequency. Another embodiment of the present invention provides a signal generator for generating a signal with a predetermined frequency. The signal generator includes a counter for generating a first count, Q_last. The counter is coupled to a ratio counter which generates a signal having a value less than or equal to Q_last. The contents of the ratio counter represent the phase of the signal having a predetermined frequency. The ratio counter outputs the signal having a predetermined frequency.

Abstract: Methods of interpolating missing pixels between interlaced scan lines is disclosed. A first method interpolates a desired pixel by selecting the median pixel from a first pixel above and to the left of the desired pixel, a second pixel above the desired pixel, a third pixel above and to the right of the desired pixel, a fourth pixel below and to the left of the desired pixel, a fifth pixel below the desired pixel, a sixth pixel below and to the right of the desired pixel, and a seventh pixel from the previous video field having same position of the desired pixel.

Abstract: A hardware apparatus for determining a median sample from n input samples is disclosed. The hardware apparatus includes n(n-1)/2 comparator circuits. The n(n-1)/2 comparator circuits compare each input sample with every other input sample. The comparator circuits are coupled to n-1 median selector circuits. Each median selector circuits selects a particular input sample as the median sample if the number of greater-than or equal-to comparisons for that particular input sample equals the number of less-than comparisons for that particular input sample.

Abstract: A clock divider circuit and a system using the same. The clock divider circuit has a clock input coupled to receive an input clock signal having an input clock frequency. Clock division logic generates an output clock signal having a fifty percent duty cycle and an output clock frequency which is an odd fraction of the input clock frequency. The clock division logic generates both the rising and the falling clock edges of the output clock signal from the input clock signal. The system disclosed includes a processor operating at a first frequency and a memory circuit coupled to exchange data with the processor. The processor includes a clock division circuit coupled to receive a first clock signal and to generate a second clock signal at a second frequency which is an odd fraction of the first frequency. The processor also includes an input/output buffer coupled to exchange data with the memory circuit.