Abstract: A method is provided. In some examples, the method includes performing, by processing circuitry, a first transform operation on a first time-domain data set to generate a frequency-domain data set. In addition, the method includes determining, by the processing circuitry, that at least one portion of the frequency-domain data set satisfies a first threshold magnitude. The method also includes performing, by the processing circuitry, an inverse transform operation on the at least one portion of the frequency-domain data set to generate a second time-domain data set. The method further includes identifying, by the processing circuitry and based on the second time-domain data set, a region of interference in the first time-domain data set.

Abstract: Aspects of the present disclosure provide for a radar system including a radar IC including a timing engine, a local oscillator, and a modulator. The timing engine is configured to generate one or more chirp control signals. The local oscillator is configured to receive the one or more chirp control signals and generate a frame including a first sequence of chirps according to the one or more chirp control signals. The modulator is configured to modulate the first sequence of chirps to generate a second sequence of chirps so the frame includes the first sequence of chirps and the second sequence of chirps offset by a first frequency value.

Abstract: A frequency-modulated continuous wave (FMCW) radar system is presented. The FMCW radar system includes a receiver configured to receive a radar reflection signal. The radar system further includes an interference detection module, which is configured to identify a portion of the radar reflection signal corresponding to the time period during which the radar reflection signal exceeds a threshold. The FMCW radar system further includes a hysteresis module configured to adjust the identified portion of the radar reflection signal based on the portion of the signal and a hysteresis configuration. The FMCW radar system further includes a mitigation module configured to mitigate interference based on the output of the hysteresis module.

Abstract: The disclosure provides a GNSS receiver. The GNSS receiver a measurement engine that generates a set of doppler measurements and a set of pseudo ranges in response to an input signal. A clock frequency drift estimation (CFDE) block receives the set of doppler measurements, and generates an averaged delta doppler. A position estimation engine estimates a position and velocity of a user based on the set of doppler measurements, the set of pseudo ranges and the averaged delta doppler.

Abstract: A radar apparatus for estimating position of a plurality of obstacles. The radar apparatus includes a receive antenna unit. The receive antenna unit includes a linear array of antennas and an additional antenna at a predefined offset from at least one antenna in the linear array of antennas. The radar apparatus also includes a signal processing unit. The signal processing unit estimates an azimuth frequency associated with each obstacle of the plurality of obstacles from a signal received from the plurality of obstacles at the linear array of antennas. In addition, the signal processing unit estimates an azimuth angle and an elevation angle associated with each obstacle from the estimated azimuth frequency associated with each obstacle.

Abstract: A method is provided. In some examples, the method includes performing, by processing circuitry, a first transform operation on a first time-domain data set to generate a frequency-domain data set. In addition, the method includes determining, by the processing circuitry, that at least one portion of the frequency-domain data set satisfies a first threshold magnitude. The method also includes performing, by the processing circuitry, an inverse transform operation on the at least one portion of the frequency-domain data set to generate a second time-domain data set. The method further includes identifying, by the processing circuitry and based on the second time-domain data set, a region of interference in the first time-domain data set.

Abstract: A radar data processing device includes at least one analog-to-digital converter (ADC) configured to digitize a plurality of input signals, wherein each input signal includes radar chirp and radar chirp reflection information received at one of a plurality of receiver antennas. The radar data processing device also includes Fast Fourier Transform (FFT) logic configured to generate FFT output samples based on each digitized input signal, wherein at least some of the generated FFT output samples are across antenna FFT output samples associated with at least two of the plurality of receiver antennas. The radar data processing device also includes a processor configured to determine a plurality of object parameters based on at least some of the generated FFT output samples, wherein the processor uses a neural network classifier trained to provide a confidence metric for at least one of the plurality of object parameters.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive, from a network node, information configuring an active bandwidth part (BWP) that does not include a bandwidth associated with one or more of a synchronization signal block (SSB) or a control resource set zero (CS0). The UE may perform, based at least in part on a radio frequency (RF) retune mode, an RF retune to a union bandwidth that covers the active BWP and the bandwidth associated with one or more of the SSB or the CS0. Numerous other aspects are described.

Abstract: An apparatus comprises processor cores and computer-readable mediums storing machine instructions for the processor cores. When executing the machine instructions, the processor cores obtain received signals for transmitted chirps from a radar sensor circuit. Each transmitted chirp comprises an A chirp segment, a time gap, and a B chirp segment, respectively. The processor cores sample the received signals to obtain sampled data matrices M1(A) for the A chirp segments and M1(B) for the B chirp segments. The processor cores perform a first Fourier transform (FT) on each column of M1(A) and M1(B) to obtain velocity matrices M2(A) and M2(B), respectively. The processor cores apply a phase compensation factor to M2(B) to obtain a phase corrected velocity matrix M2(B?), and concatenate M2(A) and M2(B?) to obtain an aggregate velocity matrix M2(A&B?). The processor cores perform a second FT on each row of M2(A&B?) to obtain a range and velocity matrix M3(A&B?).

Abstract: In an example, a method is implemented in a radar system. The method may include transmitting, via transmission channels, a frame of chirps, the chirps transmitted having a programmed frequency offset that is a function of a transmission channel of the transmission channels that is transmitting the frame of chirps, receiving, via a receive channel, a frame of reflected chirps, the reflected chirps comprising the chirps reflected by an object within a field of view of the radar system, and determining a Doppler domain representation of the frame of reflected chirps having a Doppler domain spectrum that includes multiple spectrum bands, the object represented in at least a portion of the spectrum bands based on the reflected chirps, wherein the programmed frequency is configured to cause the Doppler domain spectrum to include a number of spectrum bands greater than the number of transmission channels.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may determine whether a slot timing difference, between a first cell and a second cell for a dual connectivity mode, satisfies a threshold value, where the first cell is a serving cell associated with a first radio access technology (RAT) and the second cell is a serving cell or a candidate cell associated with a second RAT. The UE may perform an operation to prevent the dual connectivity mode with the second cell, establish the dual connectivity mode with the second cell, maintain the dual connectivity mode with the second cell, or terminate the dual connectivity mode with the second cell based at least in part on whether the slot timing difference satisfies the threshold value. Numerous other aspects are provided.

Abstract: A radar system is provided that includes a radar transceiver integrated circuit (IC) configurable to transmit a first frame of chirps, and another radar transceiver IC configurable to transmit a second frame of chirps at a time delay ?T, wherein ?T=Tc/K, K?2 and Tc is an elapsed time from a start of one chirp in the first frame and the second frame and a start of a next chirp in the first frame and the second frame, wherein the radar system is configured to determine a velocity of an object in a field of view of the radar system based on first digital intermediate frequency signals generated responsive to receiving reflected chirps of the first frame and second digital IF signals generated responsive to receiving reflected chirps of the time delayed second frame, wherein the maximum measurable velocity is increased by a factor of K.

Abstract: A radar hardware accelerator (HWA) includes a fast Fourier transform (FFT) engine including a pre-processing block for providing interference mitigation and/or multiplying a radar data sample stream received from ADC buffers within a split accelerator local memory that also includes output buffers by a pre-programmed complex scalar or a specified sample from an internal look-up table (LUT) to generate pre-processed samples. A windowing plus FFT block (windowed FFT block) is for multiply the pre-processed samples by a window vector and then processing by an FFT block for performing a FFT to generate Fourier transformed samples. A post-processing block is for computing a magnitude of the Fourier transformed samples and performing a data compression operation for generating post-processed radar data. The pre-processing block, windowed FFT block and post-processing block are connected in one streaming series data path.

Abstract: Data memory protection is provided for a signal processing system such as a radar system in which the data memory is protected with a common set of parity bits rather than requiring a set of parity bits for each memory word as in Error Correction Coded (ECC) memories. The common set of parity bits may be updated as memory words in the data memory are accessed as part of signal processing of one or more digital signals. The memory protection ensures that in the absence of memory errors the common parity bits are zero at the end of processing the digital signals as long as each word in the data memory that is used for storing the signal processing data is written and read an equal number of times.

Abstract: The described technology relates to a real-time processing of network packets. An example system relates to reordering messages received at a server over a communication network from distributed clients, in order to, among other things, eliminate or at least substantially reduce the effects of jitter (delay variance) experienced in the network. The reordering of messages may enable the example data processing application to improve the consistency of processing packets in the time order of when the respective packets entered a geographically distributed network.

Abstract: Aspects presented herein enable updating the codebook configuration upon the changing of the cover or case of the UE. The apparatus applies a first codebook from a plurality of preconfigured codebooks. The apparatus detects a change of a cover state of the UE, wherein the change alters a transmission beam pattern at the UE. The apparatus applies a second codebook from the plurality of preconfigured codebooks based on the change of the cover state.

Abstract: In accordance with described examples, a method determines if a velocity of an object detected by a radar is greater than a maximum velocity by receiving on a plurality of receivers at least one frame of chirps transmitted by at least two transmitters and reflected off of the object. A velocity induced phase shift (?d) in a virtual array vector S of signals received by each receiver corresponding to a sequence of chirps (frame) transmitted by each transmitter is estimated. Phases of each element of virtual array vector S are corrected using ?d to generate a corrected virtual array vector Sc. A first Fourier transform is performed on the corrected virtual array vector Sc to generate a corrected virtual array spectrum to detect a signature that indicates that the object has an absolute velocity greater than a maximum velocity.

Abstract: A radar system is provided that includes a radar transceiver integrated circuit (IC) configurable to transmit a first frame of chirps, and another radar transceiver IC configurable to transmit a second frame of chirps at a time delay ?T, wherein ?T=Tc/K, K?2 and Tc is an elapsed time from a start of one chirp in the first frame and the second frame and a start of a next chirp in the first frame and the second frame, wherein the radar system is configured to determine a velocity of an object in a field of view of the radar system based on first digital intermediate frequency signals generated responsive to receiving reflected chirps of the first frame and second digital IF signals generated responsive to receiving reflected chirps of the time delayed second frame, wherein the maximum measurable velocity is increased by a factor of K.

Abstract: A radar system comprises a set of transmitters and a processor coupled to the set of transmitters. The processor is configured to modulate a first portion of a chirp in a chirp frame according to a first phase. The processor is further configured to modulate a second portion of the chirp in the chirp frame according to a second phase and configured to combine the first and second portions of the chirp to produce a phase-modified chirp. The processor is further configured to instruct the set of transmitters to transmit the phase-modified chirp by applying time division multiple access (TDMA) and by directing radio frequency energy according to a target angle and a target gain.

Abstract: Methods and apparatus are disclosed low power motion detection by a radar apparatus. One example radar apparatus includes a transmitter to transmit a pattern of chirps. The transmitted pattern includes a first series of chirps transmitted during a first time period and a second series of chirps transmitted during a second time period that begins after passage of a sleep time period from an end of the first time period. The example radar apparatus also includes a receiver to detect returning chirps including reflected portions of the transmitted pattern. The example radar apparatus also includes analog to digital converter (ADC) coupled to the receiver. The ADC is to sample analog signals from the receiver to generate ADC samples for the returning chirps detected by the receiver.