Abstract: In accordance with described examples, a method determines if a velocity of an object detected by a radar is greater than a maximum velocity by receiving on a plurality of receivers at least one frame of chirps transmitted by at least two transmitters and reflected off of the object. A velocity induced phase shift (?d) in a virtual array vector S of signals received by each receiver corresponding to a sequence of chirps (frame) transmitted by each transmitter is estimated. Phases of each element of virtual array vector S are corrected using ?d to generate a corrected virtual array vector Sc. A first Fourier transform is performed on the corrected virtual array vector Sc to generate a corrected virtual array spectrum to detect a signature that indicates that the object has an absolute velocity greater than a maximum velocity.

Abstract: Data memory protection is provided for a signal processing system such as a radar system in which the data memory is protected with a common set of parity bits rather than requiring a set of parity bits for each memory word as in Error Correction Coded (ECC) memories. The common set of parity bits may be updated as memory words in the data memory are accessed as part of signal processing of one or more digital signals. The memory protection ensures that in the absence of memory errors the common parity bits are zero at the end of processing the digital signals as long as each word in the data memory that is used for storing the signal processing data is written and read an equal number of times.

Abstract: Methods for monitoring of performance parameters of one or more receive channels and/or one or more transmit channels of a radar system-on-a-chip (SOC) are provided. The radar SOC may include a loopback path coupling at least one transmit channel to at least one receive channel to provide a test signal from the at least one transmit channel to the at least one receive channel when the radar SOC is operated in test mode. In some embodiments, the loopback path includes a combiner coupled to each of one or more transmit channels, a splitter coupled to each of one or more receive channels, and a single wire coupling an output of the combiner to an input of the splitter.

Abstract: The described technology relates to a real-time order processing systems such as, for example, an electronic trading application for equities and other tradable investment instruments. An example system relates to reordering messages received at a server over a communication network from distributed clients, in order to, among other things, eliminate or at least substantially reduce the effects of jitter (delay variance) experienced in the network. The reordering of messages may enable the example electronic trading system to improve the consistency of executing orders (e.g., performing transactions for buying/selling electronic inventories) in the time order of when the client's order entered the trading system's network.

Abstract: In one embodiment, a first request may be received from a first endpoint to access a cloud-based conference platform. The first request can include a first access token. Based at least on the first request, a first certificate may be provided to the first endpoint, wherein the first certificate may not include an identity of the first endpoint. A second request may be received from a second endpoint to access the cloud-based conference platform. The second request can include a second access token. Based at least on the second request, a second certificate can be provided to the second endpoint, wherein the second certificate may not include an identity of the second endpoint. Data can be routed within the cloud-based conference platform between the first endpoint and second endpoint based at least upon the first certificate and the second certificate.

Abstract: A radar data processing device includes at least one analog-to-digital converter (ADC) configured to digitize a plurality of input signals, wherein each input signal includes radar chirp and radar chirp reflection information received at one of a plurality of receiver antennas. The radar data processing device also includes Fast Fourier Transform (FFT) logic configured to generate FFT output samples based on each digitized input signal, wherein at least some of the generated FFT output samples are across antenna FFT output samples associated with at least two of the plurality of receiver antennas. The radar data processing device also includes a processor configured to determine a plurality of object parameters based on at least some of the generated FFT output samples, wherein the processor uses a neural network classifier trained to provide a confidence metric for at least one of the plurality of object parameters.

Abstract: A user may order items that may be made available at a facility such as a pickup facility. Described are techniques for preparing and expediting an order for pick up by the user. In one implementation, geolocation data acquired from a user device may be used to determine when the user has entered a geofence associated with the facility. Based on this geolocation data and sensor data from sensors at the facility, a system may automatically identify the user. Once identified, the items in the order may be delivered to the user in a parking area of the pickup facility, who may then depart the pickup facility.

Abstract: A radar hardware accelerator (HWA) includes a fast Fourier transform (FFT) engine including a pre-processing block for providing interference mitigation and/or multiplying a radar data sample stream received from ADC buffers within a split accelerator local memory that also includes output buffers by a pre-programmed complex scalar or a specified sample from an internal look-up table (LUT) to generate pre-processed samples. A windowing plus FFT block (windowed FFT block) is for multiply the pre-processed samples by a window vector and then processing by an FFT block for performing a FFT to generate Fourier transformed samples. A post-processing block is for computing a magnitude of the Fourier transformed samples and performing a data compression operation for generating post-processed radar data. The pre-processing block, windowed FFT block and post-processing block are connected in one streaming series data path.

Abstract: A system (10) for pedestrian use includes an accelerometer (110) having multiple electronic sensors; an electronic circuit (100) operable to generate a signal stream representing magnitude of overall acceleration sensed by the accelerometer (110), and to electronically correlate a sliding window (520) of the signal stream with itself to produce peaks at least some of which represent walking steps, and further operable to electronically execute a periodicity check (540) to compare different step periods for similarity, and if sufficiently similar then to update (560) a portion of the circuit substantially representing a walking-step count; and an electronic display (190) responsive to the electronic circuit (100) to display information at least in part based on the step count. Other systems, electronic circuits and processes are disclosed.

Abstract: The disclosure provides a GNSS receiver. The GNSS receiver a measurement engine that generates a set of doppler measurements and a set of pseudo ranges in response to an input signal. A clock frequency drift estimation (CFDE) block receives the set of doppler measurements, and generates an averaged delta doppler. A position estimation engine estimates a position and velocity of a user based on the set of doppler measurements, the set of pseudo ranges and the averaged delta doppler.

Abstract: A system (10) for pedestrian use includes an accelerometer (110) having multiple electronic sensors; an electronic circuit (100) operable to generate a signal stream representing magnitude of overall acceleration sensed by the accelerometer (110), and to electronically correlate a sliding window (520) of the signal stream with itself to produce peaks at least some of which represent walking steps, and further operable to electronically execute a periodicity check (540) to compare different step periods for similarity, and if sufficiently similar then to update (560) a portion of the circuit substantially representing a walking-step count; and an electronic display (190) responsive to the electronic circuit (100) to display information at least in part based on the step count. Other systems, electronic circuits and processes are disclosed.

Abstract: A radar hardware accelerator (HWA) includes a fast Fourier transform (FFT) engine including a pre-processing block for providing interference mitigation and/or multiplying a radar data sample stream received from ADC buffers within a split accelerator local memory that also includes output buffers by a pre-programmed complex scalar or a specified sample from an internal look-up table (LUT) to generate pre-processed samples. A windowing plus FFT block (windowed FFT block) is for multiply the pre-processed samples by a window vector and then processing by an FFT block for performing a FFT to generate Fourier transformed samples. A post-processing block is for computing a magnitude of the Fourier transformed samples and performing a data compression operation for generating post-processed radar data. The pre-processing block, windowed FFT block and post-processing block are connected in one streaming series data path.

Abstract: Methods for monitoring of performance parameters of one or more receive channels and/or one or more transmit channels of a radar system-on-a-chip (SOC) are provided. The radar SOC may include a loopback path coupling at least one transmit channel to at least one receive channel to provide a test signal from the at least one transmit channel to the at least one receive channel when the radar SOC is operated in test mode. In some embodiments, the loopback path includes a combiner coupled to each of one or more transmit channels, a splitter coupled to each of one or more receive channels, and a single wire coupling an output of the combiner to an input of the splitter.

Abstract: The apparatus may be an apparatus for wireless communication. The apparatus for wireless communication may include a processing system. The processing system may manage an antenna beam. The processing system may be configured to monitor a parameter of a signal and widen the antenna beam of the apparatus for wireless communication when the parameter falls below a threshold.

Abstract: A disclosed method includes computing, for each of a plurality of values of at least one type of error parameter, a distance traveled for each of a plurality of directions of travel. The method includes selecting, from the plurality of values of the at least one type of error parameter, a value that provides a greatest distance traveled for any of the plurality of directions of travel relative to the unselected ones of the plurality of values. The method further includes applying the selected value of the at least one type of error parameter to gyroscopic sensor data, and then determining navigation information based on the gyroscopic sensor data with the selected value of the at least one type of error parameter applied.

Abstract: A method for gesture recognition includes receiving, by a processor, a first digital intermediate frequency (IF) signal stream from a first receive antenna and receiving, by the processor, a second digital IF signal stream from a second receive antenna. The method also includes computing, by the processor, a weighted Doppler metric stream based on the first digital IF signal stream and the second digital IF signal stream and computing, by the processor, an angle metric stream based on the first digital IF signal stream and the second digital IF signal stream. Additionally, the method includes computing, by the processor, a correlation between the weighted Doppler metric stream and the angle metric stream, to generate a first correlation and recognizing, by the processor, a gesture, based on the first correlation.

Abstract: Methods for monitoring of performance parameters of one or more receive channels and/or one or more transmit channels of a radar system-on-a-chip (SOC) are provided. The radar SOC may include a loopback path coupling at least one transmit channel to at least one receive channel to provide a test signal from the at least one transmit channel to the at least one receive channel when the radar SOC is operated in test mode. In some embodiments, the loopback path includes a combiner coupled to each of one or more transmit channels, a splitter coupled to each of one or more receive channels, and a single wire coupling an output of the combiner to an input of the splitter.

Abstract: The apparatus may be an apparatus for wireless communication. The apparatus for wireless communication may include a processing system. The processing system may manage an antenna beam. The processing system may be configured to monitor a parameter of a signal and widen the antenna beam of the apparatus for wireless communication when the parameter falls below a threshold.

Abstract: Disclosed examples include a radar system that operates in a first mode and a second mode. In the first mode, the system detects the presence of an object within a threshold range. In response to detection of the presence of the object, the system transitions to the second mode, and the system generates range data, velocity data, and angle data of the object in the second mode. When the object is no longer detected within the threshold range, the system transitions back to the first mode.

Abstract: A frequency modulated continuous wave (FMCW) radar system is provided that includes a receiver configured to generate a digital intermediate frequency (IF) signal, and an interference monitoring component coupled to the receiver to receive the digital IF signal, in which the interference monitoring component is configured to monitor at least one sub-band in the digital IF signal for interference, in which the at least one sub-band does not include a radar signal.