Abstract: There are provided methods of performing a photolithography process for forming asymmetric semiconductor patterns and methods of forming a semiconductor device using the same. These methods provide a way of forming asymmetric semiconductor patterns on a photoresist layer through two exposure processes. To this end, a semiconductor substrate is prepared. A planarized insulating interlayer and a photoresist layer are sequentially formed on the overall surface of the semiconductor substrate. A first semiconductor pattern of a photolithography mask is transferred to the photoresist layer, thereby forming a photoresist pattern on the photoresist layer. A second semiconductor pattern of a second photolithography mask is continuously transferred to the photoresist layer, thereby forming a second photoresist pattern on the photoresist layer.

Abstract: A semiconductor memory device may include a substrate having a plurality of active regions and a field isolation layer on the substrate surrounding the active regions of the substrate. Each of the plurality of active regions may have a length in a direction of a first axis and a width in a direction of a second axis, and the length may be greater than the width. The plurality of active regions may be provided in a plurality of columns of active regions in the direction of the second axis, and active regions of adjacent columns may be offset in the direction of the second axis.

Abstract: Methods of fabricating a semiconductor device are provided. Methods of forming a finer pattern of a semiconductor device using a buffer layer for retarding, or preventing, bridge formation between patterns in the formation of a finer pattern below resolution limits of a photolithography process by double patterning are also provided. A first hard mask layer and/or a second hard mask layer may be formed on a layer of a substrate to be etched. A first etch mask pattern of a first pitch may be formed on the second hard mask layer. After a buffer layer is formed on the overall surface of the substrate, a second etch mask pattern of a second pitch may be formed thereon in a region between the first etch mask pattern. The buffer layer may be anisotropically etched using the second etch mask pattern as an etch mask, forming a buffer layer pattern.

Abstract: A method of forming a fine pattern of a semiconductor device using a fine pitch hard mask is provided. A first hard mask pattern including first line patterns formed on an etch target layer of a substrate with a first pitch is formed. A first layer including a top surface where a recess is formed between adjacent first line patterns is formed. A second hard mask pattern including second line patterns within the recess is formed. An anisotropic etching process is performed on the first layer using the first and the second line patterns as an etch mask. Another anisotropic etching process is performed on the etch target layer using the first and the second hard mask patterns as an etch mask.

Abstract: A method of forming a fine pattern of a semiconductor device using a fine pitch hard mask is provided. A first hard mask pattern including first line patterns formed on an etch target layer of a substrate with a first pitch is formed. A first layer including a top surface where a recess is formed between adjacent first line patterns is formed. A second hard mask pattern including second line patterns within the recess is formed. An anisotropic etching process is performed on the first layer using the first and the second line patterns as an etch mask. Another anisotropic etching process is performed on the etch target layer using the first and the second hard mask patterns as an etch mask.

Abstract: Methods of forming an integrated circuit device may include forming a resist pattern on a layer of an integrated circuit device with portions of the layer being exposed through openings of the resist pattern. An organic-inorganic hybrid siloxane network film may be formed on the resist pattern. Portions of the layer exposed through the resist pattern and the organic-inorganic hybrid siloxane network film may then be removed. Related structures are also discussed.

Abstract: A photomask for measuring lens aberration, a method of manufacturing the photomask, and a method of measuring lens aberration using the photomask are provided. In an embodiment, the photomask includes a transparent substrate having first and second surfaces. A reference pattern group and an encoded pattern group are formed on the second surface of the transparent substrate, spaced apart from each other. An aperture that includes a Fresnel zone is formed to face the second surface on the second surface of the transparent substrate. Light throughput and measurement efficiency are improved.

Abstract: A method of forming a pattern for a semiconductor device is disclosed. According to the method, a lower photoresist layer is formed on a lower layer and an upper photoresist pattern including a silylated layer is formed on the lower photoresist layer. The upper photoresist pattern is used as a mask for etching the lower photoresist layer to thereby form a lower photoresist pattern. The upper and lower photoresist patterns are used as a mask for etching the lower layer beneath the lower photoresist pattern.

Abstract: Top coating compositions capable of being used in immersion lithography, and methods of forming photoresist patterns using the same, are provided. The top coating composition includes: a polymer, a base; and a solvent, wherein the polymer may be represented by Formula I: wherein R1 and R2 are independently selected from the group consisting of hydrogen, fluoro, methyl, and trifluoromethyl; X is a carboxylic acid group or a sulfonic acid group; Y is a carboxylic acid group or a sulfonic acid group, wherein the carboxylic acid group or sulfonic acid group is protected; Z is a monomer selected from the group consisting of a vinyl monomer, an alkyleneglycol, a maleic anhydride, an ethyleneimine, an oxazoline-containing monomer, acrylonitrile, an allylamide, a 3,4-dihydropyran, a 2,3-dihydrofuran, tetrafluoroethylene, or a combination thereof; and m, n, and q are integers wherein 0.03?m/(m+n+q)?0.97, 0.03?n/(m+n+q)?0.97, 0?q/(m+n+q)?0.5; and wherein the solvent includes deionized water.

Abstract: Methods of forming an integrated circuit device may include forming a resist pattern on a layer of an integrated circuit device with portions of the layer being exposed through openings of the resist pattern. An organic-inorganic hybrid siloxane network film may be formed on the resist pattern. Portions of the layer exposed through the resist pattern and the organic-inorganic hybrid siloxane network film may then be removed. Related structures are also discussed.

Abstract: A mask pattern for semiconductor device fabrication comprises a resist pattern formed on a semiconductor substrate, and an interpolymer complex film formed on the resist pattern, wherein the interpolymer complex film includes a network formed by a hydrogen bond between a proton donor polymer and a proton acceptor polymer.

Abstract: A method of forming an underlayer of a bi-layer resist including forming a blended material by blending a polymer having an aromatic group and a methacrylate polymer, and coating a substrate with the blended material. The blended material coated on the substrate is irradiated to form an underlayer. The polymer having the aromatic group may be a novolac polymer or a naphthalene polymer.

Abstract: A composition for a bottom-layer resist, having superior anti-refractivity and dry-etch resistance for use in a bi-layer resist process employing a light source at a wavelength of 193 nm or below, is disclosed. The composition for the bottom-layer resist contains a polymer represented by formula 1: In formula 1, R is hydrogen or a methyl group, m/(m+n) is about 0.5 to about 1.0 and n/(m+n) is 0 to about 0.5.

Abstract: A mask pattern for semiconductor device fabrication comprises a resist pattern formed on a semiconductor substrate, and an interpolymer complex film formd on the resist pattern, wherein the interpolymer complex film includes a network formed by a hydrogen bond between a proton donor polymer and a proton acceptor polymer.

Abstract: A semiconductor device includes a substrate, and a plurality of active pillars arranged in a pattern of alternating even and odd rows and alternating even and odd columns, each active pillar extending from the substrate and including a channel portion, wherein the odd columns include active pillars spaced at a first pitch, the first pitch being determined in the column direction, the even columns include active pillars spaced at the first pitch, the even rows include active pillars spaced at a third pitch, the third pitch being determined in the row direction the odd rows include active pillars spaced at the third pitch, and active pillars in the even columns are offset by a second pitch from active pillars in the odd columns, the second pitch being determined in the column direction.

Abstract: An organic anti-reflective coating (ARC) is formed over a surface of a semiconductor substrate, and a resist layer including a photosensitive polymer is formed on the ARC. The photoresistive polymer contains a hydroxy group. The resist layer is then subjected to exposure and development to form a resist pattern. The resist pattern to then silylated to a given depth by exposing a surface of the resist pattern to a vapor phase organic silane mixture of a first organic silane compound having a functional group capable of reacting with the hydroxy group of the photoresistive polymer, and a second organic silane compound having two functional groups capable of reacting with the hydroxy group of the photoresistive polymer Then, the silylated resist pattern is thermally treated, and the organic ARC is an isotropically etched using the thermally treated resist pattern as an etching mask.

Abstract: There are provided a method of forming a trench for a recessed channel of a transistor and a layout for the same. A layout for the recessed channel according to one aspect of the present invention is formed such that an open region is extended across at least one of a first active region in a lateral direction, and also across another second active region in parallel with the first active region in a diagonal direction, and the extension is cut not to reach an isolation region between two third active regions that are in parallel with the second active region in a diagonal direction, and have noses facing each other in a longitudinal direction, and the layout includes an alignment of a plurality of open regions, which are discontinuously aligned. An etch mask is formed using the layout, and a semiconductor substrate is etched using the etch mask, and a trench for a recessed channel is formed on the active region.

Abstract: A reflective photomask for EUV light is disclosed. The reflective photomask may include a projecting pattern selectively formed on a substrate and a reflective layer on the substrate and the projecting pattern.

Abstract: A resist composition includes a photoacid generator (PAG) and a photosensitive polymer. The photosensitive polymer is polymerized with (a) at least one of the monomers having the respective formulae: where R1 and R2 are independently a hydrogen atom, alkyl, hydroxyalkyl, alkyloxy, carbonyl or ester, and x and y are independently integers from 1 to 6, and (b) at least one of a (meth)acrylate monomer, a maleic anhydride monomer, and a norbornene monomer.

Abstract: A polymer, a top coating layer, a top coating composition and an immersion lithography process using the same are disclosed. The top coating layer polymer may include a deuterated carboxyl group having a desired acidity such that the top coating layer polymer may be insoluble with water and a photoresist, and soluble in a developer. The polymer may be included in a top coating layer and a top coating composition.