Patents by Inventor Sang-hoon Ahn
Sang-hoon Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210233860Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.Type: ApplicationFiled: April 14, 2021Publication date: July 29, 2021Inventors: SU-HYUN BARK, SANG-HOON AHN, YOUNG-BAE KIM, HYEOK-SANG OH, WOO-JIN LEE, HOON-SEOK SEO, SUNG-JIN KANG
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Publication number: 20210233862Abstract: A semiconductor may include a first inter metal dielectric (IMD) layer, a first blocking layer on the first IMD layer, a metal wiring and a second blocking layer. The first inter metal dielectric (IMD) layer may be formed on a substrate, the first IMD layer may include a low-k material having a dielectric constant lower than a dielectric constant of silicon oxide. The first blocking layer may be formed on the first IMD layer. The first blocking layer may include an oxide having a dielectric constant higher than the dielectric constant of the first IMD layer. The metal wiring may be through the first IMD layer and the first blocking layer. The second blocking layer may be formed on the metal wiring and the first blocking layer. The second blocking layer may include a nitride. The first and second blocking layers may reduce or prevent from the out gassing, so that a semiconductor device may have good characteristics.Type: ApplicationFiled: April 13, 2021Publication date: July 29, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Jun-Kwan KIM, Jae-Wha PARK, Sang-Hoon AHN
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Patent number: 11049810Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.Type: GrantFiled: June 21, 2019Date of Patent: June 29, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Su-Hyun Bark, Sang-Hoon Ahn, Young-Bae Kim, Hyeok-Sang Oh, Woo-Jin Lee, Hoon-Seok Seo, Sung-Jin Kang
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Patent number: 11037872Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the semiconductor device including a substrate; a first insulating interlayer on the substrate; a first wiring in the first insulating interlayer on the substrate; an insulation pattern on a portion of the first insulating interlayer adjacent to the first wiring, the insulation pattern having a vertical sidewall and including a low dielectric material; an etch stop structure on the first wiring and the insulation pattern; a second insulating interlayer on the etch stop structure; and a via extending through the second insulating interlayer and the etch stop structure to contact an upper surface of the first wiring.Type: GrantFiled: April 4, 2019Date of Patent: June 15, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyu-Hee Han, Jong-Min Baek, Hoon-Seok Seo, Sang-Hoon Ahn, Woo-Jin Lee
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Patent number: 11011469Abstract: A semiconductor may include a first inter metal dielectric (IMD) layer, a first blocking layer on the first IMD layer, a metal wiring and a second blocking layer. The first inter metal dielectric (IMD) layer may be formed on a substrate, the first IMD layer may include a low-k material having a dielectric constant lower than a dielectric constant of silicon oxide. The first blocking layer may be formed on the first IMD layer. The first blocking layer may include an oxide having a dielectric constant higher than the dielectric constant of the first IMD layer. The metal wiring may be through the first IMD layer and the first blocking layer. The second blocking layer may be formed on the metal wiring and the first blocking layer. The second blocking layer may include a nitride. The first and second blocking layers may reduce or prevent from the out gassing, so that a semiconductor device may have good characteristics.Type: GrantFiled: February 26, 2019Date of Patent: May 18, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Kwan Kim, Jae-Wha Park, Sang-Hoon Ahn
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Patent number: 10950845Abstract: Provided is a battery protection circuit module package capable of easily achieving high integration and size reduction. The battery protection circuit module package includes a terminal lead frame including a first internal connection terminal lead and a second internal connection terminal lead provided at two edges of the terminal lead frame and electrically connected to electrode terminals of a battery bare cell, and a plurality of external connection terminal leads provided between the first and second internal connection terminal leads and serving as a plurality of external connection terminals, and a device package including a substrate mounted on the terminal lead frame to be electrically connected to the terminal lead frame, and providing a battery protection circuit device thereon.Type: GrantFiled: January 22, 2019Date of Patent: March 16, 2021Assignee: ITM SEMICONDUCTOR CO., LTDInventors: Ho-seok Hwang, Young-Seok Kim, Seong-beom Park, Sang-hoon Ahn, Tae Hwan Jung, Seung-uk Park, Jae-ku Park, Myoung-Ki Moon, Hyun-suck Lee, Da-Woon Jung
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Patent number: 10916437Abstract: Provided herein is a method of forming micropatterns, including: forming an etching target film on a substrate; forming a photosensitivity assisting layer on the etching target film, the photosensitivity assisting layer being terminated with a hydrophilic group; forming an adhesive layer on the photosensitivity assisting layer, the adhesive layer forming a covalent bond with the hydrophilic group; forming a hydrophobic photoresist film on the adhesive layer; and patterning the photoresist film.Type: GrantFiled: December 27, 2018Date of Patent: February 9, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Shin Jang, Jong-Min Baek, Hoon-Seok Seo, Eui-Bok Lee, Sung-Jin Kang, Vietha Nguyen, Deok-Young Jung, Sang-Hoon Ahn, Hyeok-Sang Oh, Woo-Kyung You
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Publication number: 20210014976Abstract: A method of fabricating a battery protection circuit package according to one aspect of the present invention includes forming a first mounting structure by mounting battery protection circuit elements on a printed circuit board (PCB), forming a second mounting structure by mounting the first mounting structure on a lead frame which comprises an input/output terminal portion for external connection and at least one metal tab for battery cell connection, forming an encapsulation structure by encapsulating the second mounting structure with a molding material to encapsulate at least a part of the battery protection circuit elements while exposing the input/output terminal portion and the at least one metal tab of the lead frame, and bonding at least one flexible printed circuit board (FPCB) to the input/output terminal portion of the encapsulation structure.Type: ApplicationFiled: June 22, 2020Publication date: January 14, 2021Inventors: Hyuk Hwi NA, Ho Seok HWANG, Young Seok KIM, Sang Hoon AHN, Jae Ku PARK, Sung Hee WANG, Eun Bin LEE
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Patent number: 10867923Abstract: A semiconductor device includes an element layer, a plurality of first interconnect lines on the element layer, a first insulation layer including carbon having a uniform concentration distribution between the first interconnect lines, a plurality of second interconnect lines spaced from the first interconnect lines, and a second insulation layer between the second interconnect lines. An air spacing is included between the second interconnect lines.Type: GrantFiled: September 19, 2018Date of Patent: December 15, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang Hoon Ahn, Tae Soo Kim, Jong Min Baek, Woo Kyung You, Thomas Oszinda, Byung Hee Kim, Nae In Lee
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Patent number: 10847454Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a first insulating film on the substrate, a lower metal layer in the first insulating film, and a second insulating film on the first insulating film. The lower metal layer may be in the second insulating film, the second insulating film may include a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film may be upwardly convex. The semiconductor devices may further include a barrier dielectric film including a recess on the second insulating film, and a via metal layer that is in the recess of the barrier dielectric film and electrically connected with the lower metal layer.Type: GrantFiled: December 16, 2019Date of Patent: November 24, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Eui Bok Lee, Deok Young Jung, Sang Bom Kang, Doo-Hwan Park, Jong Min Baek, Sang Hoon Ahn, Hyeok Sang Oh, Woo Kyung You
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Patent number: 10840564Abstract: According to an aspect of the present invention, there is provided a battery protection circuit module including a first positive terminal and a first negative terminal electrically connected to electrode terminals of a battery bare cell, a second positive terminal and a second negative terminal electrically connected to a charger or an electronic device, a first protection circuit unit including a first single field-effect transistor connected between at least one of the first positive and negative terminals and at least one of the second positive and negative terminals, and a first protection integrated circuit (P-IC) for controlling the first single field-effect transistor, and a second protection circuit unit including a second single field-effect transistor connected between at least one of the first positive and negative terminals and at least one of the second positive and negative terminals, and a second P-IC for controlling the second single field-effect transistor.Type: GrantFiled: August 11, 2016Date of Patent: November 17, 2020Assignee: ITM SEMICONDUCTOR CO., LTD.Inventors: Hyuk Hwi Na, Ho Seok Hwang, Young Seok Kim, Sang Hoon Ahn
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Patent number: 10756550Abstract: According to an aspect of the present invention, there is provided a battery protection circuit module including a first positive terminal and a first negative terminal electrically connected to electrode terminals of a battery bare cell, a second positive terminal and a second negative terminal electrically connected to a charger or an electronic device, a single field-effect transistor including a drain terminal, a source terminal, a gate terminal, and a well terminal, wherein the drain terminal is electrically connected to the first negative terminal and the source terminal is electrically connected to the second negative terminal, and a protection integrated circuit (P-IC) for controlling charging/discharging of the battery bare cell by controlling the gate terminal to control whether to switch on the single field-effect transistor and controlling a bias voltage of the well terminal by using an internal switch.Type: GrantFiled: August 11, 2016Date of Patent: August 25, 2020Assignee: ITM SEMICONDUCTOR CO., LTD.Inventors: Hyuk Hwi Na, Ho Seok Hwang, Young Seok Kim, Sang Hoon Ahn
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Patent number: 10700164Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.Type: GrantFiled: February 13, 2019Date of Patent: June 30, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Nam Kim, Rak-Hwan Kim, Byung-Hee Kim, Jong-Min Baek, Sang-Hoon Ahn, Nae-In Lee, Jong-Jin Lee, Ho-Yun Jeon, Eun-Ji Jung
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Publication number: 20200118926Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a first insulating film on the substrate, a lower metal layer in the first insulating film, and a second insulating film on the first insulating film. The lower metal layer may be in the second insulating film, the second insulating film may include a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film may be upwardly convex. The semiconductor devices may further include a barrier dielectric film including a recess on the second insulating film, and a via metal layer that is in the recess of the barrier dielectric film and electrically connected with the lower metal layer.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Inventors: Eui Bok LEE, Deok Young JUNG, Sang Bom KANG, Doo-Hwan PARK, Jong Min BAEK, Sang Hoon AHN, Hyeok Sang OH, Woo Kyung YOU
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Publication number: 20200105664Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the semiconductor device including a substrate; a first insulating interlayer on the substrate; a first wiring in the first insulating interlayer on the substrate; an insulation pattern on a portion of the first insulating interlayer adjacent to the first wiring, the insulation pattern having a vertical sidewall and including a low dielectric material; an etch stop structure on the first wiring and the insulation pattern; a second insulating interlayer on the etch stop structure; and a via extending through the second insulating interlayer and the etch stop structure to contact an upper surface of the first wiring.Type: ApplicationFiled: April 4, 2019Publication date: April 2, 2020Inventors: Kyu-Hee HAN, Jong-Min BAEK, Hoon-Seok SEO, Sang-Hoon AHN, Woo-Jin LEE
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Publication number: 20200035613Abstract: A semiconductor may include a first inter metal dielectric (IMD) layer, a first blocking layer on the first IMD layer, a metal wiring and a second blocking layer. The first inter metal dielectric (IMD) layer may be formed on a substrate, the first IMD layer may include a low-k material having a dielectric constant lower than a dielectric constant of silicon oxide. The first blocking layer may be formed on the first IMD layer. The first blocking layer may include an oxide having a dielectric constant higher than the dielectric constant of the first IMD layer. The metal wiring may be through the first IMD layer and the first blocking layer. The second blocking layer may be formed on the metal wiring and the first blocking layer. The second blocking layer may include a nitride. The first and second blocking layers may reduce or prevent from the out gassing, so that a semiconductor device may have good characteristics.Type: ApplicationFiled: February 26, 2019Publication date: January 30, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Jun-Kwan KIM, Jae-Wha PARK, Sang-Hoon AHN
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Patent number: 10535600Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a lower wiring, a first interlayer insulating film disposed on the substrate and including a first region and a second region over the first region, an etch stop film on the first interlayer insulating film, a second interlayer insulating film on the etch stop film, a first upper wiring in the second interlayer insulating film, the etch stop film, and the second region of the first interlayer insulating film and the first upper wiring is spaced apart from the lower wiring and a via in the first region of the first interlayer insulating film, and the via connects the lower wiring and the first upper wiring, wherein the first upper wiring includes a first portion in the second interlayer insulating film, and a second portion in the etch stop film and the second region of the first interlayer insulating film, and a sidewall of the second portion of the first upper wiring includes a stepwise shape.Type: GrantFiled: May 23, 2018Date of Patent: January 14, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hoon Seok Seo, Jong Min Baek, Su Hyun Bark, Sang Hoon Ahn, Hyeok Sang Oh, Eui Bok Lee
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Patent number: 10529618Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes forming a first insulting layer on a substrate, forming a first conductor pattern in the first insulating layer, forming a second insulating layer on the first insulating layer, and forming a second wiring pattern and a contact via in the second insulating layer, wherein a top surface of the first insulating layer is higher than a top surface of the first conductor pattern.Type: GrantFiled: January 12, 2018Date of Patent: January 7, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Siqing Lu, Sang-Hoon Ahn, Xinglong Chen, Ki-Hyun Kim, Kyu-In Shim
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Patent number: 10510658Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a first insulating film on the substrate, a lower metal layer in the first insulating film, and a second insulating film on the first insulating film. The lower metal layer may be in the second insulating film, the second insulating film may include a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film may be upwardly convex. The semiconductor devices may further include a barrier dielectric film including a recess on the second insulating film, and a via metal layer that is in the recess of the barrier dielectric film and electrically connected with the lower metal layer.Type: GrantFiled: July 19, 2018Date of Patent: December 17, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Eui Bok Lee, Deok Young Jung, Sang Bom Kang, Doo-Hwan Park, Jong Min Baek, Sang Hoon Ahn, Hyeok Sang Oh, Woo Kyung You
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Patent number: 10497649Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.Type: GrantFiled: December 5, 2017Date of Patent: December 3, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Su-Hyun Bark, Sang-Hoon Ahn, Young-Bae Kim, Hyeok-Sang Oh, Woo-Jin Lee, Hoon-Seok Seo, Sung-Jin Kang