Abstract: An integrated circuit (IC) device includes a lower wiring structure including a lower metal film. The lower wiring structure penetrates at least a portion of a first insulating film disposed over a substrate. The IC device further includes a capping layer covering a top surface of the lower metal film, a second insulating film covering the capping layer, an upper wiring structure penetrating the second insulating film and the capping layer, and electrically connected to the lower metal film, and an air gap disposed between the lower metal film and the second insulating film. The air gap has a width defined by a distance between the capping layer and the upper wiring structure.

Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.

Abstract: According to an aspect of the present invention, there is provided a battery protection circuit module including a first positive terminal and a first negative terminal electrically connected to electrode terminals of a battery bare cell, a second positive terminal and a second negative terminal electrically connected to a charger or an electronic device, a first protection circuit unit including a first single field-effect transistor connected between at least one of the first positive and negative terminals and at least one of the second positive and negative terminals, and a first protection integrated circuit (P-IC) for controlling the first single field-effect transistor, and a second protection circuit unit including a second single field-effect transistor connected between at least one of the first positive and negative terminals and at least one of the second positive and negative terminals, and a second P-IC for controlling the second single field-effect transistor.

Abstract: According to an aspect of the present invention, there is provided a battery protection circuit module including a first positive terminal and a first negative terminal electrically connected to electrode terminals of a battery bare cell, a second positive terminal and a second negative terminal electrically connected to a charger or an electronic device, a single field-effect transistor including a drain terminal, a source terminal, a gate terminal, and a well terminal, wherein the drain terminal is electrically connected to the first negative terminal and the source terminal is electrically connected to the second negative terminal, and a protection integrated circuit (P-IC) for controlling charging/discharging of the battery bare cell by controlling the gate terminal to control whether to switch on the single field-effect transistor and controlling a bias voltage of the well terminal by using an internal switch.

Abstract: A method of forming a semiconductor device can include forming an insulation layer using a material having a composition selected to provide resistance to subsequent etching process. The composition of the material can be changed to reduce the resistance of the material to the subsequent etching process at a predetermined level in the insulation layer. The subsequent etching process can be performed on the insulation layer to remove an upper portion of the insulation layer above the predetermined level and leave a lower portion of the insulation layer below the predetermined level between adjacent conductive patterns extending through the lower portion of the insulation layer. A low-k dielectric material can be formed on the lower portion of the insulation layer between the adjacent conductive patterns to replace the upper portion of the insulation layer above the predetermined level.

Abstract: A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.

Abstract: A pedestal of a CVD apparatus includes a raised central portion, a peripheral portion extending around the central portion, and a carrier ring support disposed along the peripheral portion. A carrier ring of the CVD apparatus includes an annular body disposed over the peripheral portion of the pedestal. The carrier ring is mounted to the pedestal by virtue of the carrier ring support, and in such a way that a lower surface of the annular body is spaced vertically from the peripheral portion of the pedestal and the carrier ring is separable from the pedestal in a vertical direction. A drive mechanism cooperates with carrier ring to lift the carrier ring of the pedestal and mount the carrier ring back onto the pedestal.

Abstract: A semiconductor device includes an insulating interlayer on a first region of a substrate. The insulating interlayer has a recess therein and includes a low-k material having porosity. A damage curing layer is formed on an inner surface of the recess. A barrier pattern is formed on the damage curing layer. A copper structure fills the recess and is disposed on the barrier pattern. The copper structure includes a copper pattern and a copper-manganese capping pattern covering a surface of the copper pattern. A diffusion of metal in a wiring structure of the semiconductor device may be prevented, and thus a resistance of the wiring structure may decrease.

Abstract: Provided is a battery protection circuit package capable of effectively preventing overcurrent and overheating and of being implemented at low costs in a compact size, the battery protection circuit package including a first terminal and a second terminal electrically connected to electrode terminals of a battery bare cell, a third terminal and a fourth terminal electrically connected to a charger or an electronic device, a first protection circuit module including one or more first transistors connected between at least one of the first and second terminals and at least one of the third and fourth terminals, and a first protection integrated circuit (IC) for controlling the one or more first transistors, and a second protection circuit module including one or more second transistors connected between at least one of the first and second terminals and at least one of the third and fourth terminals and connected in series to the one or more first transistors, and a second protection IC for controlling the one

Abstract: A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.

Abstract: A protection IC includes a bias output terminal connected to a back gate of a MOS transistor, a load side terminal connected to a power supply path between a load and the MOS transistor, a load side switch inserted in an electric current path connecting the bias output terminal and the load side terminal, and a control circuit configured to control the load side switch based on a state of a secondary battery and thereby cause a back gate control signal for controlling a voltage of the back gate to be output from the bias output terminal. The load side switch is formed on an N-type silicon substrate and includes at least two NMOS transistors whose drains are connected to each other, and the control circuit is configured to simultaneously turn on or turn off the two NMOS transistors based on the state of the secondary battery.

Abstract: A secondary battery protection circuit includes a first terminal connected to a power supply path between a secondary battery and a MOS transistor, a second terminal connected to the power supply path between a load and the MOS transistor, a third terminal connected to a gate of the MOS transistor, a fourth terminal connected to a back gate of the MOS transistor, a control circuit that outputs a switch control signal based on a detected abnormal state of the secondary battery, and a switch control circuit including a first switch for connecting the fourth terminal with the first terminal and a second switch for connecting the fourth terminal with the second terminal. At least one of the resistance between the fourth terminal and the first terminal and the resistance between the fourth terminal and the second terminal is greater than the on resistance value of the MOS transistor.

Abstract: A semiconductor device may include a plurality of wiring structures spaced apart from each other, a protection pattern including a metal nitride on each of the wiring structures, a spacer on a sidewall of the protection pattern, and an insulating interlayer structure containing the wiring structures and having an air gap between the wiring structures.

Abstract: Disclosed is a reamer for implant surgery including: cutting front end portions each of which has a sharp front end; cut edges of a horizontal line form, the cutting front end portions and the cut edges being arranged radially and alternately, wherein one side of the cutting front end portion having the sharp front end has a triangular depressed face inclined downwardly toward a rotation central axis of the cutting part, and one side of the cut edge having the horizontal line form has a triangular inclined face inclined downwardly toward the outer circumferential surface of the cutting part, wherein an inclination angle of a side inclined edge inclined downwardly at the sides of the outer circumferences of the cutting front end portion and the cut edge becomes gradually smaller in the rotation direction of the cutting part.

Abstract: A semiconductor device includes a plurality of wiring structures spaced apart from each other, and an insulating interlayer structure. Each of the wiring structures includes a metal pattern and a barrier pattern covering a sidewall, a bottom surface, and an edge portion of a top surface of the metal pattern and not covering a central portion of the top surface of the metal pattern. The insulating interlayer structure contains the wiring structures therein, and has an air gap between the wiring structures.

Abstract: A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.

Abstract: A semiconductor device includes a first conductive pattern on a substrate, an insulating diffusion barrier layer conformally covering a surface of the first conductive pattern, the insulation diffusion barrier layer exposed by an air gap region adjacent to a sidewall of the first conductive pattern, and a second conductive pattern on the first conductive pattern, the second conductive pattern penetrating the insulating diffusion barrier layer so as to be in contact with the first conductive pattern.

Abstract: A semiconductor device includes a substrate, a conductive pattern, a side spacer, and an air gap. The substrate includes an interlayer insulating layer and a trench penetrating the interlayer insulating layer. The conductive pattern is disposed within the trench of the substrate. The side spacer is disposed within the trench. The side spacer covers an upper side surface of the conductive pattern. The air gap is disposed within the trench. The air gap is bounded by a sidewall of the trench, the side spacer, and a lower side surface of the conductive pattern. A level of a bottom surface of the conductive pattern is lower than a level of bottom surfaces of the side spacer.

Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

Abstract: Disclosed is a battery protection module package (PMP). The battery PMP according to an embodiment of the present invention includes a lead frame provided with a plurality of external terminals thereon, a printed circuit board stacked on the lead frame, and a plurality of internal terminals, a protection integrated chip (IC), a field effect transistor (FET), resistors, and capacitors disposed on the printed circuit board and electrically connected to each other, wherein the resistors and the capacitors are mounted on a pattern of the printed circuit board using surface mount technology (SMT), and wherein the plurality of internal terminals are electrically connected to the plurality of external terminals.