Abstract: Methods and apparatus for self testing a multiband voltage controlled oscillator (VCO) are disclosed. A tuning voltage of the VCO is adjusted where the output of the VCO does not affect the input to the VCO. Frequency bands in the VCO are selected. Output frequencies of the VCO are measured.

Abstract: Techniques for setting a fine tuning input signal Vtune for a voltage-controlled oscillator (VCO) in a coarse tuning mode of the VCO. In an exemplary embodiment, the fine tuning input signal during coarse tuning mode is made temperature-dependent to account for possible variation of Vtune over temperature during fine tuning mode. Methods and apparatuses employing the techniques are further described.

Abstract: Techniques for improving the linearity of a cascode amplifier. In an exemplary embodiment, an auxiliary common-gate amplifier is provided in parallel with the principal cascode branch. The auxiliary common-gate amplifier samples a cascoded node in the principal cascode branch. The auxiliary common-gate amplifier generates a current which, when combined with the current generated by the principal cascode branch, cancels a distortion component to generate an output current with improved linearity characteristics. In an exemplary embodiment, a phase shifting network couples the cascoded node to the auxiliary common-gate amplifier, and may include, e.g., a capacitor coupled to an inductor.

Abstract: A method for fabricating a semiconductor device improves the variation in critical dimensions of neighboring patterns when employing a negative SPT process. The method includes forming an etch stop layer on an etch target layer, forming a first hard mask pattern on the etch stop layer, forming a spacer pattern on a sidewall of the first hard mask pattern, forming a second hard mask layer on an entire surface of a resultant structure including the spacer pattern, forming a second hard mask pattern by etching the second hard mask layer up to a height of the first hard mask pattern, removing the spacer pattern, and forming a pattern by etching the etch stop layer and the etch target layer using the first and the second hard mask patterns as an etch barrier.

Abstract: Techniques for reducing or eliminating DC (direct current) offset in transmitters are disclosed. An apparatus for DC offset reduction may include a converter, a digital engine, and a plurality of programmable current supplies. The converter is configured to provide digital representations of a plurality of DC currents associated, respectively, with a plurality of differential signal legs. The digital engine is configured to receive the digital representations and to produce instructions for generating compensating currents for the plurality of differential signal legs based on comparisons, respectively, between each of the digital representations and a calibration current. The programmable current supplies correspond, respectively, to the differential signal legs. The current supplies are configured to inject the compensating currents into the differential signal legs, respectively, to reduce DC offset between the differential signal legs, based upon the instructions.

Abstract: Techniques are disclosed for trimming a capacitance associated with a capacitor bank for use in a voltage-controlled oscillator (VCO). In an embodiment, each capacitance is sub-divided into a plurality of constituent capacitances. The constituent capacitances may be selectively enabled or disabled to trim the step sizes of the capacitor bank. Further techniques are disclosed for calibrating the trimmable capacitance to minimize step size error for the capacitor bank.

Abstract: Techniques for compensating for the effects of temperature change on voltage controlled oscillator (VCO) frequency are disclosed. In an embodiment, an auxiliary varactor is coupled to an LC tank of the VCO. The auxiliary varactor has a capacitance controlled by a temperature-dependant control voltage to minimize the overall change in VCO frequency with temperature. Techniques for generating the control voltage using digital and analog means are further disclosed.

Abstract: A method for fabricating a capacitor in a semiconductor device includes forming a stack structure providing a plurality of open regions, the stack structure including an insulation layer and a hard mask pattern, forming a conductive layer over the stack structure and in the open regions, etching a portion of the conductive layer formed outside the open regions to form bottom electrodes in the open regions, removing the hard mask pattern, and etching upper portions of the bottom electrodes that are exposed after the hard mask pattern is removed.

Abstract: A method for forming a contact hole of a semiconductor device includes: forming a lower pattern over a substrate; forming a spin-on-glass (SOG) layer over the lower pattern; performing a first curing process on the SOG layer; forming an opening exposing a portion of the SOG layer; performing a second curing process on the SOG layer corresponding to a lower portion of the opening; and forming a contact hole exposing the lower pattern.

Abstract: In one embodiment of the invention, a method for a charge pump is disclosed. The method includes biasing a plurality of transistors; switching a pair of main transistor switches to apply or remove a net charge on an output terminal though the biased transistors; and turning on auxiliary transistor switches when the main transistor switches are turned off. The auxiliary transistor switches when turned on provide an auxiliary equalizing path to nodes between the main transistor switches and the biased transistors. The auxiliary equalizing path equalizes voltages between the intermediate nodes to rapidly turn off the biased transistors and reduce noise on the output terminal of the charge pump.

Abstract: A circuit which selects a supply voltage from a plurality of voltage supplies is presented. The circuit includes a first transistor configured to select a first voltage supply, a second transistor configured to select a second voltage supply, a first parasitic current inhibitor coupled the first transistor, the first voltage supply, and the second voltage supply, where the first parasitic current inhibitor automatically utilizes the voltage supply providing the highest voltage for preventing a substrate current from flowing through a bulk node of the first transistor, and a second parasitic current inhibitor coupled the second transistor, the first voltage supply, and the second voltage supply, where the second parasitic current inhibitor automatically utilizes the voltage supply providing the highest voltage for preventing a substrate current from flowing through a bulk node of the second transistor.

Abstract: A method for fabricating a semiconductor device includes providing a substrate, forming an insulation layer over the substrate, forming a photoresist pattern for a contact hole over the insulation layer, wherein the photoresist pattern includes an opening having a critical dimension (CD) greater than a desired contact CD, forming a contact hole by selectively etching the insulation layer using the photoresist pattern, and forming a spacer on a sidewall of the contact hole until a CD of the contact hole whose sidewall is covered by the spacer is reduced to a desired contact CD.

Abstract: A method for fabricating a capacitor in a semiconductor device includes forming a stack structure providing a plurality of open regions, the stack structure including an insulation layer and a hard mask pattern, forming a conductive layer over the stack structure and in the open regions, etching a portion of the conductive layer formed outside the open regions to form bottom electrodes in the open regions, removing the hard mask pattern, and etching upper portions of the bottom electrodes that are exposed after the hard mask pattern is removed.

Abstract: A method for forming a contact hole of a semiconductor device includes: forming a lower pattern over a substrate; forming a spin-on-glass (SOG) layer over the lower pattern; performing a first curing process on the SOG layer; forming an opening exposing a portion of the SOG layer; performing a second curing process on the SOG layer corresponding to a lower portion of the opening; and forming a contact hole exposing the lower pattern.

Abstract: A system and method are disclosed for configuring a frequency synthesizer in a transceiver. Configuring a frequency synthesizer in a transceiver includes specifying a selection bit sequence wherein the selection bit sequence corresponds to a predetermined combination of transceiver characteristics; determining a plurality of synthesizer configuration parameters using the selection bit sequence; and configuring the frequency synthesizer using the plurality of synthesizer configuration parameters.

Abstract: A fractional-N frequency synthesizer includes a voltage-controlled oscillator, a dual-modulus divider which divides an output frequency of the voltage-controlled oscillator according to a fractional control input, and a phase comparator which compares a phase of an output of the dual-modulus divider with a phase of a reference frequency, where an output of the phase comparator controls an input of the voltage-controlled oscillator. The synthesizer further includes a sigma-delta modulator which has a single-bit output, and a bit converter which converts the single-bit output of the sigma-delta modulator to the fractional control input applied to the dual-modulus divider.

Abstract: A sigma delta modulator system and a method for modulating a signal are described. The sigma delta modulator includes a plurality of cascading stages, an output coupled to the plurality of the cascading stages via a plurality of feedback connections, and a feedforward connection coupled between a selected one of the plurality of cascading stages and a point closer to the output interface of the sigma delta modulator.

Abstract: An input buffer circuit includes a first amplifier having low load impedance and a second amplifier having high load impedance. The output signals of the input buffer circuit have wide bandwidth, although the input buffer circuit has two stage amplifiers. In addition, the bandwidth can be controlled by resistors as an equivalent active inductance of the input buffer circuit. Further, the input buffer circuit can reduce the power consumption compared with conventional input buffer circuits, since the input buffer circuit according to the present invention uses a first switching current of the first amplifier as well as a second switching current of the second amplifier to load output signals.

Abstract: An input buffer circuit includes a first amplifier having low load impedance and a second amplifier having high load impedance. The output signals of the input buffer circuit have wide bandwidth, although the input buffer circuit has two stage amplifiers. In addition, the bandwidth can be controlled by resistors as an equivalent active inductance of the input buffer circuit. Further, the input buffer circuit can reduce the power consumption compared with conventional input buffer circuits, since the input buffer circuit according to the present invention uses a first switching current of the first amplifier as well as a second switching current of the second amplifier to load output signals.

Abstract: A power-on reset circuit is provided for generating a power-on reset signal for sequential logics or memory devices as a power supply potential is applied initially. The power-on reset circuit is provided in the same chip as the sequential logics, and generates the signal after an adjustable time interval. The power-on reset circuit includes an oscillator for generating a clock signal, and a counter for counting pulses of the clock signal from when the power supply potential is applied. The time interval is adjusted by loading a preset data value in the counter, which thus outputs a CTR signal when the counted pulses become equal in number to the preset number. A combinational logic circuit resets the counter when the power supply potential is initially applied, and also generates a power-on reset signal when the counter outputs the CTR signal. The power on reset signal further disables the counter, so that the CTR signal is maintained.