Patents by Inventor Sang Yun Lee

Sang Yun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11983374
    Abstract: A touch sensor may include a substrate and may include electrode units, first demultiplexers, second demultiplexers, and driving pads all located on the substrate. The electrode units each may include a plurality of electrode groups, the electrode groups each including a plurality of touch electrodes. The first demultiplexers each may include a plurality of sub-demultiplexers and each may be electrically connected to a corresponding one of the electrode units. Each of the sub-demultiplexers of a first demultiplexer may be electrically connected to a corresponding one of the electrode groups of a corresponding electrode unit. The second demultiplexers may be connected between the first demultiplexers and the driving pads.
    Type: Grant
    Filed: May 1, 2023
    Date of Patent: May 14, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hwa Jeong Kim, Jae Sic Lee, Na Yun Kwak, Dong Hwan Kim, Seung Woo Sung, Min Kyu Woo, Min Ku Lee, Seong Jun Lee, Sang Jin Pak, Sang Hyun Jun
  • Publication number: 20240150191
    Abstract: In a method for recovering lithium hydroxide from a lithium secondary battery, cathode powder is prepared from a cathode of the lithium secondary battery. A cathode active material mixture is prepared by mixing the cathode powder with a calcium compound. The cathode active material mixture is reduced to form a preliminary precursor mixture. A lithium precursor is recovered from the preliminary precursor mixture. Therefore, a lithium precursor can be obtained with high purity without a complicated leaching process or an additional process, which result from a wet-based acid solution process.
    Type: Application
    Filed: March 3, 2022
    Publication date: May 9, 2024
    Inventors: Young Bin SEO, Ji Yun PARK, Sung Real SON, Sang Ick LEE, Suk Joon HONG, Ji Min KIM
  • Publication number: 20240155775
    Abstract: A lend moving apparatus includes a circuit board including a mounting groove, an image sensor arranged within the mounting groove of the circuit board, and a first epoxy arranged within the mounting groove. The mounting groove includes a first side surface and a second side surface that face each other, and a third side surface and a fourth side surface that face each other. The circuit board includes at least one application groove provided on the first side surface and/or the second side surface of the mounting groove. The at least one application groove includes an opening opened toward the upper surface of the circuit board. At least a portion of the first epoxy is arranged in the at least one application groove.
    Type: Application
    Filed: January 12, 2024
    Publication date: May 9, 2024
    Applicant: LG INNOTEK CO.,LTD.
    Inventors: Do Yun KIM, Seong Min LEE, Eun Mi KIM, Sang Ok PARK
  • Publication number: 20240154013
    Abstract: Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.
    Type: Application
    Filed: January 8, 2024
    Publication date: May 9, 2024
    Applicant: BeSang, Inc.
    Inventor: Sang-Yun Lee
  • Patent number: 11976155
    Abstract: The present disclosure relates to an expanded foam solution for forming a thermosetting expanded foam having excellent flame retardancy produced using the same. According to the present disclosure, nanoclay is mixed with a polyol-based compound using ultrasonic waves, an isocyanate-based compound is added, and a trimerization catalyst or an isocyanurate compound is mixed with the polyol-based compound so that an isocyanurate structure is formed.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: May 7, 2024
    Assignee: KYUNG DONG ONE CORPORATION
    Inventors: Jong Hyun Yoon, Sang Yun Lee, Dae Woo Nam
  • Patent number: 11977855
    Abstract: The Zero User Interface (UI)-based automatic speech translation system and method can solve problems such as the procedural inconvenience of inputting speech signals and the malfunction of speech recognition due to crosstalk when users who speak difference languages have a face-to-face conversation. The system includes an automatic speech translation server, speaker terminals and a counterpart terminal. The automatic speech translation server selects a speech signal of a speaker among multiple speech signals received from speaker terminals connected to an automatic speech translation service and transmits a result of translating the speech signal of the speaker into a target language to a counterpart terminal.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: May 7, 2024
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sang Hun Kim, Seung Yun, Min Kyu Lee, Joon Gyu Maeng, Dong Hyun Kim
  • Patent number: 11978777
    Abstract: Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: May 7, 2024
    Assignee: BeSang, Inc.
    Inventor: Sang-Yun Lee
  • Patent number: 11966631
    Abstract: A method and system for maintaining command queue order are disclosed. According to certain embodiments, commands are read from a host, storing command queue IDs in an array that will keep the queue IDs in order. After having the queue IDs stored in the array, the commands are processed in the data storage device (DSD). After processing, the commands are provided to a completion order adjustment module that will order the commands in queue ID order for sequential commands to be returned to the host. In certain embodiments, for a sequential command, other commands of the same sequence are searched for the array and ordered with the sequential command. If a particular command of the sequence is not found, the completion order adjustment module will wait to transfer the sequence until each command of the sequence is found. For commands not part of a sequence, these commands are transferred to the host.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: April 23, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sang Yun Jung, Min Woo Lee, Min Young Kim
  • Patent number: 11961775
    Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.
    Type: Grant
    Filed: November 8, 2022
    Date of Patent: April 16, 2024
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Gyu Wan Han, Won Bae Bang, Ju Hyung Lee, Min Hwa Chang, Dong Joo Park, Jin Young Khim, Jae Yun Kim, Se Hwan Hong, Seung Jae Yu, Shaun Bowers, Gi Tae Lim, Byoung Woo Cho, Myung Jea Choi, Seul Bee Lee, Sang Goo Kang, Kyung Rok Park
  • Publication number: 20240115107
    Abstract: Disclosed herein is a mobile cleaning device with a sterilization function.
    Type: Application
    Filed: October 24, 2022
    Publication date: April 11, 2024
    Applicant: KOREA ENVIRONMENTAL INDUSTRY CO., LTD
    Inventor: Sang Yun LEE
  • Publication number: 20240105255
    Abstract: A semiconductor memory device includes a memory bank arranged into first through nth split regions containing at least one memory cell sub-array within each split region, and first through nth global input/output (GIO) split lines electrically coupled to the first through nth split regions. First through n-lth connection control transistors are provided, which have gate terminals responsive to respective connection control signals. The first connection control transistor is configured to electrically short the first and second GIO split lines together when enabled by a corresponding connection control signal, and the n-1th connection control transistor is configured to electrically short the n-1th and nth GIO split lines together when enabled by a corresponding connection control signal. A GIO sense amplifier is provided, which is electrically coupled to the memory bank.
    Type: Application
    Filed: May 24, 2023
    Publication date: March 28, 2024
    Inventors: Seung-Jun Lee, Sang-Yun Kim, Jonghyuk Kim, Bok-Yeon Won
  • Patent number: 11941845
    Abstract: An apparatus for estimating a camera pose according to an embodiment of the present disclosure includes a similar image searcher, a clusterer, and an estimator. The similar image searcher searches for a plurality of images similar to an input image, from among a plurality of previously-stored images, based on the input image. The clusterer creates a cluster including at least some similar images meeting predetermined conditions, from among the plurality of similar images, based on viewpoint data tagged to each of the plurality of similar images. The estimator estimates a pose of a camera that has generated the input image, based on the cluster.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: March 26, 2024
    Assignee: MAXST CO., LTD.
    Inventors: Sang Rok Kim, Kyu Sung Cho, Jae Wan Park, Tae Yun Son, Hyung Min Lee
  • Patent number: 11930684
    Abstract: Provided is a display device. The display device includes a first base portion, a second base portion facing the first base portion, a light emitting layer disposed on one surface of the first base portion and emitting first light, a first wavelength conversion pattern disposed on the light emitting layer and converting the first light into second light having a different wavelength from the first light, a first color filter overlapping the first wavelength conversion pattern on one surface of the second base portion and spaced apart from the first wavelength conversion pattern, and an air layer interposed between the first wavelength conversion pattern and the first color filter.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: March 12, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Chang Soon Jang, Keun Chan Oh, Gak Seok Lee, Sang Hun Lee, So Yun Lee, Ji Eun Jang
  • Publication number: 20240079043
    Abstract: An operating method of a memory device, comprising: entering self-refresh section, updating a counting code by counting an edge of a reference cycle signal, first activating an operation control signal for the self-refresh section when a temperature application code has an initialized value in response to the counting code, updating the temperature application code after the operation control signal is first activated, second activating the operation control signal in response to the counting code based on the updated temperature application code, exiting from the self-refresh section, and initializing the counting code and the temperature application code.
    Type: Application
    Filed: February 9, 2023
    Publication date: March 7, 2024
    Inventors: Sang Hoon LEE, Sang Jin BYEON, Kyo Yun LEE
  • Patent number: 11925026
    Abstract: Disclosed are novel structures and methods for 3D NVM built with vertical transistors above a logic layer. A first embodiment has a conductive film under the transistors and serving as a common node in a memory block. The conductive film may be from a semiconductor layer used to build the transistors. Metal lines are disposed above the transistors for connection through 3D vias to underlying circuitry. Contact plugs may be formed between transistors and metal lines. The conductive film may be coupled to underlying circuitry through contacts on the conductive film or through interconnect vias underneath the film. A second embodiment has conductive lines disposed under the transistors. Either of conductive lines and metal lines may serve as source lines and the other as bit lines for the memory. For low parasitic resistances, the conductive lines may be shorted to bypass metal lines residing in underlying logic layer.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: March 5, 2024
    Inventor: Sang-Yun Lee
  • Patent number: 11914564
    Abstract: A Merkle tree-based data management method may comprise: aligning data into two-dimensional square matrix; calculating a hash value of each node of the two-dimensional square matrix; calculating hash values of each row of the two-dimensional square matrix; generating an additional column with nodes having the hash values of each row; calculating hash values of each column of the two-dimensional square matrix; generating an additional row with nodes having hash values of each column; and calculating a Merkle root by concatenating the hash values of the additional column and the hash values of the additional row.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: February 27, 2024
    Assignee: Penta Security Inc.
    Inventors: Jin Hyeok Oh, Keon Yun, Sun Woo Yun, Sang Min Lee, Jun Yong Lee, Sang Gyoo Sim, Tae Gyun Kim
  • Publication number: 20240021689
    Abstract: Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.
    Type: Application
    Filed: August 11, 2023
    Publication date: January 18, 2024
    Applicant: BeSang, Inc.
    Inventor: Sang-Yun Lee
  • Publication number: 20230349140
    Abstract: Disclosed is a toilet bowl bidet capable of preventing droplets from splashing, the toilet bowl bidet including a washing water supply hose (150) having an air pump (180) disposed at an outlet side of a washing water valve (160) and configured to mix air into washing water supplied to a bidet nozzle unit (140), wherein the bidet nozzle unit (140) includes first and second washing water passages (141) and (143) respectively including bidet nozzles (142) and (144), a third washing water passage (145) including a shield nozzle (146), and a distributor 148 configured to guide the washing water to a selected one of the first, second, and third washing water passages (141), (143), and (145). A controller (170) is configured to, when a flushing operation is performed, control the distributor (148) to supply air-mixed washing water to the third washing water passage (145) and open the washing water valve (160).
    Type: Application
    Filed: July 6, 2023
    Publication date: November 2, 2023
    Inventors: Sang Yun LEE, Pil Won BONG, Heung Soon LEE
  • Publication number: 20230331897
    Abstract: The present disclosure relates to an expanded foam solution for forming a thermosetting expanded foam having excellent flame retardancy produced using the same. According to the present disclosure, nanoclay is mixed with a polyol-based compound using ultrasonic waves, an isocyanate-based compound is added, and a trimerization catalyst or an isocyanurate compound is mixed with the polyol-based compound so that an isocyanurate structure is formed.
    Type: Application
    Filed: June 16, 2023
    Publication date: October 19, 2023
    Inventors: Jong Hyun YOON, Sang Yun LEE, Dae Woo NAM
  • Patent number: 11769809
    Abstract: Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: September 26, 2023
    Assignee: BESANG, INC.
    Inventor: Sang-Yun Lee