Abstract: A method for fabricating a field effect transistor device comprises forming a fin on a substrate, forming a first dummy gate stack and a second dummy gate stack over the fin, forming spacers adjacent to the fin, the first dummy gate stack, and the second dummy gate stack, etching to remove portions of the fin and form a first cavity partially defined by the spacers, depositing an insulator material in the first cavity, patterning a mask over the first dummy gate stack and portions of the fin, etching to remove exposed portions of the insulator material, and epitaxially growing a first semiconductor material on exposed portions of the fin.

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

Abstract: A method of forming a punch through stop region in a fin structure is disclosed. The method may include forming a doped glass layer on a fin structure and forming a masking layer on the doped glass layer. The method may further include removing a portion of the masking layer from an active portion of the fin structure, and removing an exposed portion the doped glass layer that is present on the active portion of the fin structure. A remaining portion of the doped glass layer is present on the isolation portion of the fin structure. Dopant from the doped glass layer may then be diffused into the isolation portion of the fin structure to form the punch through stop region between the active portion of the fin structure and a supporting substrate.

Abstract: A method of forming a semiconductor device that includes providing a vertically orientated channel region; and converting a portion of an exposed source/drain contact surface of the vertically orientated channel region into an amorphous crystalline structure. The amorphous crystalline structure is from the vertically orientated channel region. An in-situ doped extension region is epitaxially formed on an exposed surface of the vertically orientated channel region. A source/drain region is epitaxially formed on the in-situ doped extension region.

Abstract: A bilayer of silicon dioxide and silicon nitride is formed on exposed surfaces of at least one semiconductor fin having a bottom source/drain region located at the footprint, and on each side, of the at least one semiconductor fin. An upper surface of each horizontal portion of the silicon nitride layer is then carbonized, and thereafter non-carbonized vertical portions of the silicon nitride layer are removed. Next, the carbonized portions of the silicon nitride layer are removed, and thereafter the vertical portions of the silicon dioxide layer are removed from sidewalls of the at least one semiconductor fin utilizing each remaining portion of the silicon nitride layer as an etch mask A bottom spacer structure is provided on each bottom source/drain region in which each bottom spacer structure includes a remaining portion of the silicon dioxide layer and the remaining portion of the silicon nitride layer.

Abstract: A bilayer of silicon dioxide and silicon nitride is formed on exposed surfaces of at least one semiconductor fin having a bottom source/drain region located at the footprint, and on each side, of the at least one semiconductor fin. An upper surface of each horizontal portion of the silicon nitride layer is then carbonized, and thereafter non-carbonized vertical portions of the silicon nitride layer are removed. Next, the carbonized portions of the silicon nitride layer are removed, and thereafter the vertical portions of the silicon dioxide layer are removed from sidewalls of the at least one semiconductor fin utilizing each remaining portion of the silicon nitride layer as an etch mask A bottom spacer structure is provided on each bottom source/drain region in which each bottom spacer structure includes a remaining portion of the silicon dioxide layer and the remaining portion of the silicon nitride layer.

Abstract: After forming a gate stack straddling a portion of each semiconductor fin of a plurality of semiconductor fins located over a substrate, a gate liner is formed on sidewalls of a lower portion of the gate stack that contacts the plurality of semiconductor fins and a gate spacer having a width greater than a width of the gate liner is formed on sidewalls of an upper portion of the gate stack that is located above the plurality of semiconductor fins. The width of the gate spacer thus is not limited by the fin pitch, and can be optimized to improve the device performance.

Abstract: A method of forming an improved field-effect transistor device is provided. The method includes forming a tensile stressor near a first semiconductor fin. The first semiconductor fin is a fin of an n-channel field-effect transistor. The n-channel field-effect transistor is formed on a substrate. The method also includes forming a compressive stressor near a second semiconductor fin. The second semiconductor fin is a fin of a p-channel field effect transistor. The p-channel field-effect transistor is formed on the substrate. The method can also include forming neutral material over the at least one n-channel and p-channel field effect transistor. The method can also include achieving different device performance by configuring a stressor distance to fin and/or by configuring a stressor volume.

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

Abstract: A method of forming a spacer for a vertical transistor is provided. The method includes forming a fin structure on a substrate, depositing a first spacer on exposed surfaces of the substrate to define gaps between the first spacer and the fin structure and depositing a second spacer on the exposed surfaces of the substrate in at least the gaps.

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

Abstract: A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2.

Abstract: A method for forming a semiconductor device comprising forming a semiconductor fin on a substrate, forming a first sacrificial gate stack over a first channel region of the fin and forming a second sacrificial gate stack over a second channel region of the fin, forming spacers adjacent to the first sacrificial gate stack and the second sacrificial gate stack, depositing a first liner layer on the spacers, the first sacrificial gate stack and the second sacrificial gate stack, depositing a first sacrificial layer on the first liner layer, removing a portion of the first sacrificial layer over the first gate stack to expose a portion of the first liner layer on the first sacrificial gate stack, and growing a first semiconductor material on exposed portions of the fin to form a first source/drain region adjacent to the first gate sacrificial gate stack.

Abstract: A method of filling trenches between gates includes forming a first and a second dummy gate over a substrate, the first and second dummy gates including a sacrificial gate material and a hard mask layer; forming a first gate spacer along a sidewall of the first dummy gate and a second gate spacer along a sidewall of the second dummy gate; performing an epitaxial growth process to form a source/drain on the substrate between the first and second dummy gates; disposing a conformal liner over the first and second dummy gates and the source/drain; disposing an oxide on the conformal liner between the first and second dummy gates; recessing the oxide to a level below the hard mask layers of the first and second dummy gates to form a recessed oxide; and depositing a spacer material over the recessed oxide between the first dummy gate and the second dummy gate.

Abstract: A method for forming a semiconductor device comprising forming a semiconductor fin on a substrate, forming a first sacrificial gate stack over a first channel region of the fin and forming a second sacrificial gate stack over a second channel region of the fin, forming spacers adjacent to the first sacrificial gate stack and the second sacrificial gate stack, depositing a first liner layer on the spacers, the first sacrificial gate stack and the second sacrificial gate stack, depositing a first sacrificial layer on the first liner layer, removing a portion of the first sacrificial layer over the first gate stack to expose a portion of the first liner layer on the first sacrificial gate stack, and growing a first semiconductor material on exposed portions of the fin to form a first source/drain region adjacent to the first gate sacrificial gate stack.

Abstract: A method of forming a punch through stop region in a fin structure is disclosed. The method may include forming a doped glass layer on a fin structure and forming a masking layer on the doped glass layer. The method may further include removing a portion of the masking layer from an active portion of the fin structure, and removing an exposed portion the doped glass layer that is present on the active portion of the fin structure. A remaining portion of the doped glass layer is present on the isolation portion of the fin structure. Dopant from the doped glass layer may then be diffused into the isolation portion of the fin structure to form the punch through stop region between the active portion of the fin structure and a supporting substrate.

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

Abstract: A method of forming a spacer for a vertical transistor is provided. The method includes forming a fin structure on a substrate, depositing a first spacer on exposed surfaces of the substrate to define gaps between the first spacer and the fin structure and depositing a second spacer on the exposed surfaces of the substrate in at least the gaps.

Abstract: Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.

Abstract: Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.