Patents by Inventor Sanjay Wadhwa

Sanjay Wadhwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120290721
    Abstract: A network device may include logic to establish an IP session, establish a BFD session within the established IP session, transmit BFD packets within the established BFD session, and determine that the established IP session is active based upon reception of the BFD packets. In another embodiment, the logic may also determine that an IP session is active using an inactivity timer that may also trigger transmission of BFD packets.
    Type: Application
    Filed: July 24, 2012
    Publication date: November 15, 2012
    Applicant: JUNIPER NETWORKS, INC.
    Inventors: Vitali VINOKOUR, Sanjay WADHWA, Jerome MOISAND
  • Patent number: 8260902
    Abstract: An example network device includes network interfaces and a control unit that receives a network configuration request from a client device and sends a network configuration response to the client device.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: September 4, 2012
    Assignee: Juniper Networks, Inc.
    Inventors: Kathryn DeGraaf, Paul Raison, John Liddy, John C. Scano, Sanjay Wadhwa
  • Patent number: 8255543
    Abstract: A network device may include logic to establish an IP session, establish a BFD session within the established IP session, transmit BFD packets within the established BFD session, and determine that the established IP session is active based upon reception of the BFD packets. In another embodiment, the logic may also determine that an IP session is active using an inactivity timer that may also trigger transmission of BFD packets.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: August 28, 2012
    Assignee: Juniper Networks, Inc.
    Inventors: Vitali Vinokour, Sanjay Wadhwa, Jerome Moisand
  • Patent number: 8121126
    Abstract: The invention is directed towards techniques for forwarding subscriber frames through a Multi-Protocol Label Switching (MPLS) aggregation network using MPLS labels. Layer two (L2) network devices, such as access nodes, of a service provider (SP) network implement MPLS functionality in the data plane, but do not implement an MPLS signaling protocol in the control plane. The L2 network devices include an interface for configuring a static pool of labels applied in the data plane of the L2 network device to output MPLS communications to the MPLS network. The access nodes may be configured by an administrator to maintain static pools of subscriber labels and MPLS labels. The access nodes autonomously allocate the subscriber labels to subscriber devices that request broadband services from a Broadband Services Router (BSR), and distribute the subscriber labels and MPLS labels as upstream assigned labels.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: February 21, 2012
    Assignee: Juniper Networks, Inc.
    Inventors: Jerome P. Moisand, Rahul Aggarwal, Sanjay Wadhwa, Benjamin Hickey
  • Patent number: 8085791
    Abstract: The invention is directed towards techniques for forwarding subscriber frames through a Multi-Protocol Label Switching (MPLS) aggregation network using MPLS labels. Layer two (L2) network devices, such as access nodes, of a service provider (SP) network implement MPLS functionality in the data plane, but do not implement an MPLS signaling protocol in the control plane. The L2 network devices include a pool of labels applied in the data plane of the L2 network device to output MPLS communications to the MPLS network, and a protocol that allows a layer three (L3) device to control provision of L2 functionality by the L2 device. The pool of labels is dynamically configured by the L3 device via the protocol. The access nodes distribute the subscriber labels and MPLS labels as upstream assigned labels.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: December 27, 2011
    Assignee: Juniper Networks, Inc.
    Inventors: Rahul Aggarwal, Benjamin Hickey, Sanjay Wadhwa, Jerome P. Moisand
  • Patent number: 8086713
    Abstract: In general, techniques are described for automatically releasing network resources reserved for use by network devices within a network. In particular, a network device, such as a router, may include an interface card that receives a first and a second message from respective first and second client devices requesting reservation of network resources. The first message may include a first identifier, while the second message may include a second identifier. Both messages however may also include the same additional context information that identifies the same context in which the first client device operates. The router may include a control unit that determines whether the additional context information included within the first and second messages is the same. Based on a determination that this information is the same, the control unit may automatically release resources reserved for use by the first client device within the network.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: December 27, 2011
    Assignee: Juniper Networks, Inc.
    Inventors: Sunil Gandhewar, Sanjay Wadhwa, William Townsend, John Liddy
  • Publication number: 20110154440
    Abstract: A method performed by a Dynamic Host Configuration Protocol (DHCP) server comprising receiving a DHCP DISCOVER message from a DHCP client; generating a challenge in response to the DHCP DISCOVER message; sending the challenge to an authentication device; receiving a first challenge response from the authentication device; generating a DHCP OFFER message; sending the challenge to the DHCP client in the DHCP OFFER message; receiving a DHCP REQUEST message that includes a second challenge response from the DHCP client; comparing the first challenge response with the second challenge response; and authenticating the DHCP client when the first challenge response and the second challenge response match.
    Type: Application
    Filed: December 22, 2009
    Publication date: June 23, 2011
    Applicant: JUNIPER NETWORKS, INC.
    Inventors: Kathryn DE GRAAF, John LIDDY, Paul RAISON, John C. SCANO, Sanjay WADHWA
  • Publication number: 20110066735
    Abstract: A network device may include logic to establish an IP session, establish a BFD session within the established IP session, transmit BFD packets within the established BFD session, and determine that the established IP session is active based upon reception of the BFD packets. In another embodiment, the logic may also determine that an IP session is active using an inactivity timer that may also trigger transmission of BFD packets.
    Type: Application
    Filed: November 22, 2010
    Publication date: March 17, 2011
    Applicant: JUNIPER NETWORKS, INC.
    Inventors: Vitali VINOKOUR, Sanjay Wadhwa, Jerome Moisand
  • Patent number: 7860981
    Abstract: A network device may include logic to establish an IP session, establish a BFD session within the established IP session, transmit BFD packets within the established BFD session, and determine that the established IP session is active based upon reception of the BFD packets. In another embodiment, the logic may also determine that an IP session is active using an inactivity timer that may also trigger transmission of BFD packets.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: December 28, 2010
    Assignee: Juniper Networks, Inc.
    Inventors: Vitali Vinokour, Sanjay Wadhwa, Jerome Moisand
  • Patent number: 7786809
    Abstract: A system that includes a phase locked loop and an activation circuit; wherein the phase locked loop includes an oscillator, a frequency divider, a phase detector, a control circuit, and a memory circuit. The activation circuit is adapted to activate the memory circuit and the oscillator; to deactivate the frequency divider, the phase detector and the control circuit during deactivation periods and to activate the frequency divider, the phase detector and the control circuit during activation periods. The timing relationship between a deactivation period and an activation period is responsive to an output signal jitter limitation and to a power consumption limitation.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: August 31, 2010
    Assignee: Freescale
    Inventors: Michael Priel, Lavi Koch, Sanjay Wadhwa
  • Publication number: 20100191813
    Abstract: In general, techniques are described for automatically releasing network resources reserved for use by network devices within a network. In particular, a network device, such as a router, may include an interface card that receives a first and a second message from respective first and second client devices requesting reservation of network resources. The first message may include a first identifier, while the second message may include a second identifier. Both messages however may also include the same additional context information that identifies the same context in which the first client device operates. The router may include a control unit that determines whether the additional context information included within the first and second messages is the same. Based on a determination that this information is the same, the control unit may automatically release resources reserved for use by the first client device within the network.
    Type: Application
    Filed: February 6, 2009
    Publication date: July 29, 2010
    Inventors: Sunil Gandhewar, Sanjay Wadhwa, William Townsend, John Liddy
  • Patent number: 7715391
    Abstract: Methods and systems consistent with the present invention provide a way to provide optimal delivery of multicast content by retail ISPs in a wholesale aggregation network environment. A broadband network gateway dynamically informs an access node of a mapping between a multicast domain corresponding to the retail service provider, allowing the gateway to send multicast data to the access node for replication to subscribers instead of replicating the multicast data at the gateway. The gateway dynamically informs the access node of the mapping using a standardized access node control protocol. The gateway can also dynamically instruct the access node to update or delete the mapping.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: May 11, 2010
    Assignee: Juniper Networks, Inc.
    Inventors: Sanjay Wadhwa, Derek Harkness
  • Publication number: 20090279701
    Abstract: A network controls provision of access functionality by an access node to provide a network service to a subscriber device. For example, the network device may control the queuing and forwarding of packets by the access node to facilitate packet transmission according to, for example, a Quality of Service class. The network device may send control messages to the access node to dynamically configure a control object stored by the access node, such as a Quality of Service profile. The network device may be a router, and the access node may be a base station that wireless communicates with a subscriber device, e.g., a cellular phone. The access node may then delivery the packets in accordance with the dynamically configured control object.
    Type: Application
    Filed: July 21, 2009
    Publication date: November 12, 2009
    Applicant: Juniper Networks, Inc.
    Inventors: Jerome Moisand, Sanjay Wadhwa, Dilip Pillaipakkamnatt
  • Publication number: 20090205024
    Abstract: Methods and systems consistent with the present invention provide a dynamic mechanism to support wholesale access for broadband subscribers. This mechanism involves dynamically discovering a retail ISP for a subscriber, and dynamically cross-connecting a subscriber's connection to a logical connection corresponding to a retail ISP, and is equally applicable to static, PPP and DHCP-based subscribers. Furthermore, dynamic steering of subscribers can be performed at layer 2 or layer 3 of the OSI model.
    Type: Application
    Filed: February 12, 2008
    Publication date: August 13, 2009
    Applicant: JUNIPER NETWORKS, INC.
    Inventors: Mathias Kokot, Sanjay Wadhwa, Brian M. Sullivan
  • Publication number: 20080018368
    Abstract: A brown out detector includes a first resistive element connected to a first voltage and a first node. A capacitor is connected to the first node and a second voltage. The detector also includes a second transistor and a third transistor. The second transistor has a drain connected to a second node, a source connected to the first node, and a gate connected to the first voltage. The third transistor has a source connected to the second voltage and the capacitor, a drain connected to the second node, and a gate connected to the first voltage. The detector also includes a latch having an input connected to the second node and a detector output, which generates a reset signal when the first voltage is less than a detection threshold voltage.
    Type: Application
    Filed: September 14, 2007
    Publication date: January 24, 2008
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Sanjay WADHWA, Siddhartha G.K.
  • Publication number: 20080012603
    Abstract: A brown out detector includes a first resistive element connected to a first voltage and a first node. A capacitor is connected to the first node and a second voltage. The detector also includes a second transistor and a third transistor. The second transistor has a drain connected to a second node, a source connected to the first node, and a gate connected to the first voltage. The third transistor has a source connected to the second voltage and the capacitor, a drain connected to the second node, and a gate connected to the first voltage. The detector also includes a latch having an input connected to the second node and a detector output, which generates a reset signal when the first voltage is less than a detection threshold voltage.
    Type: Application
    Filed: July 17, 2006
    Publication date: January 17, 2008
    Inventors: Sanjay Wadhwa, Siddhartha G.K.
  • Publication number: 20070080724
    Abstract: A digital clock frequency multiplier (100) for increasing an input frequency of an input clock signal includes a generator (102) that receives the input clock signal and a high frequency digital signal. The generator (102) divides a count (Nhf) of a number of cycles of the high frequency digital signal in one period of the input clock signal by a predetermined multiplication factor (MF) for generating an output clock signal. The output clock signal has a predetermined output frequency.
    Type: Application
    Filed: October 3, 2006
    Publication date: April 12, 2007
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Sanjay Wadhwa, Deeya Muhury, Pawan Tiwari
  • Publication number: 20070018864
    Abstract: A compensation circuit and a method that compensates for process, voltage and temperature (PVT) variations in an integrated circuit that includes functional modules. The compensation circuit includes a signal generator, a first code generator, a second code generator, and a mapping module. The signal generator generates a first signal and a second signal depending on aligned process corner, voltage and temperature variations and skewed process corner variations respectively. The first code generator receives the first signal, and generates a first calibration code. The second code generator receives the second signal, and generates a second calibration code. The mapping module provides the first and second calibration codes for compensating for the aligned process corner, voltage and temperature variations and the skewed process corner variations associated with the functional modules respectively.
    Type: Application
    Filed: July 20, 2006
    Publication date: January 25, 2007
    Inventors: Qadeer Khan, Sanjay Wadhwa, Divya Tripathi, Siddhartha Gk, Kulbhushan Misri
  • Publication number: 20070018712
    Abstract: A compensation circuit and a method for compensating for process, voltage and temperature (PVT) variations in an integrated circuit (IC). The IC includes several functional modules, each of which includes a set of functional units, and generates an output signal in response to an input signal. The compensation circuit includes a code generator and a logic module. The code generator generates a digital code for each functional unit. The digital codes are based on phase differences between the input signal and the output signal. The logic module generates calibration codes based on the digital codes. The calibration codes compensate for the PVT variations in the corresponding functional units.
    Type: Application
    Filed: July 20, 2006
    Publication date: January 25, 2007
    Inventors: Siddhartha GK, Qadeer Khan, Divya Tripathi, Sanjay Wadhwa, Kulbhushan Misri
  • Publication number: 20070018713
    Abstract: A compensation circuit and a method for detecting and compensating for process, voltage, and temperature (PVT) variations in an integrated circuit. The integrated circuit includes plural logic modules that include PMOS transistors and NMOS transistors. The compensation circuit includes first and second functional modules, which generate first and second calibration signals. The first and the second calibration signals are used to compensate for the PVT variations in PMOS and NMOS transistors.
    Type: Application
    Filed: July 20, 2006
    Publication date: January 25, 2007
    Inventors: Divya Tripathi, Siddhartha Gk, Qadeer Khan, Kulbhushan Misri, Sanjay Wadhwa