Abstract: A digital clock frequency doubler for increasing an input frequency of an input clock signal includes an input block, and a generator block. The input block receives the input clock signal, and generates a pulse signal having an ON period equal to the input clock signal period. The generator block is coupled to the input block. The generator block receives the pulse signal and divides a period of the pulse signal by a period of a high frequency digital signal and then generates an output clock signal with an output frequency that is about two times the input frequency.

Abstract: A power on reset (POR) circuit for providing a reset pulse signal to a chip when power supply voltage, VDD, ramps up so that the chip always starts in a known state. The POR circuit generates the reset pulse as soon as VDD exceeds an assertion voltage. The assertion voltage is independent of the ramp rate of VDD. The POR circuit is shut off as soon as the reset signal is generated, thereby drawing zero steady state current from VDD. The re-arm time for the POR circuit is very small. The POR circuit does not reset the chip when there is a dynamic change in VDD.

Abstract: A band-gap reference circuit for generation of voltages and currents independent of process, voltage, and temperature includes three inversely proportional to absolute temperature (IPTAT) current generators. The IPTAT current generators generate three currents that are added to generate a current independent of the absolute temperature. The generated current is passed through a switched capacitor resistor to generate the band-gap reference voltage across the switched capacitor resistor.

Abstract: A bi-directional level shifter for shifting a digital signal from a low power supply voltage level to a high power supply voltage level and vice versa includes first and second I/O terminals, a first circuit operating at a low power supply voltage, and a second circuit operating at a high power supply voltage. The first circuit and the second circuit are connected to both of the I/O terminals. When a low voltage digital signal is applied at the first I/O terminal, a high voltage digital signal is generated at the second I/O terminal. Similarly, if a high voltage digital signal is applied at the second I/O terminal, a low voltage digital signal is generated at the first I/O terminal.

Abstract: A power on reset (POR) circuit for providing a reset pulse signal to a chip when power supply voltage, VDD, ramps up so that the chip always starts in a known state. The POR circuit generates the reset pulse as soon as VDD exceeds an assertion voltage. The assertion voltage is independent of the ramp rate of VDD. The POR circuit is shut off as soon as the reset signal is generated, thereby drawing zero steady state current from VDD. The re-arm time for the POR circuit is very small. The POR circuit does not reset the chip when there is a dynamic change in VDD.

Abstract: A level shifter that shifts a low supply voltage input signal to a higher supply voltage output signal includes a first unit and a second unit. The first unit is connected to a high power supply voltage source and receives the input signal. The first unit acts as a startup circuit such that when the level shifter is switched on, the first unit discharges an output node if the input signal is a logic low, and when the input signal is a logic high, the first unit charges a control node to the voltage of the input signal. The second unit is connected to the first unit and the high power supply voltage source, and also receives the input signal. The second unit shifts the input signal to the higher supply voltage output signal. The level shifter operates only at the high power supply voltage.

Abstract: A bi-directional level shifter for shifting a digital signal from a low power supply voltage level to a high power supply voltage level and vice versa includes first and second I/O terminals, a first circuit operating at a low power supply voltage, and a second circuit operating at a high power supply voltage. The first circuit and the second circuit are connected to both of the I/O terminals. When a low voltage digital signal is applied at the first I/O terminal, a high voltage digital signal is generated at the second I/O terminal. Similarly, if a high voltage digital signal is applied at the second I/O terminal, a low voltage digital signal is generated at the first I/O terminal.