Patents by Inventor Satoru KAMEYAMA
Satoru KAMEYAMA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9627323Abstract: A semiconductor device comprises a conductive layer, a first insulating film, a barrier metal, a contact electrode, and a surface electrode. The first insulating film is located on the conductive layer and comprises a contact hole reaching the conductive layer. At least a surface part of the first insulating film is a BPSG film. The barrier metal covers an inner surface of the contact hole. The contact electrode is located in the contact hole and on the barrier metal. The surface electrode is located on the BPSG film and the contact electrode. The barrier metal is not interposed between the BPSG film and the surface electrode so that the surface electrode is directly in contact with the BPSG film. At least a part of the surface electrode is a bonding pad.Type: GrantFiled: November 20, 2015Date of Patent: April 18, 2017Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Shinya Iwasaki, Satoru Kameyama
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Publication number: 20170092714Abstract: A structure having high, middle, and low impurity concentration regions disposed from a surface side of a substrate is more suitably manufactured. A method of manufacturing a semiconductor device includes: a first implantation of first conductivity type impurities into a first conductivity type semiconductor substrate from a surface; melting and solidifying a first semiconductor region between a depth and the surface, wherein the depth is deeper than a depth having a peak impurity concentration in an increased region where the impurity concentration was increased in the first implantation, and shallower than a deeper end of the increased region; a second implantation of the impurities from the surface into a region shallower than the depth; and melting and solidifying a region in which the impurity concentration was increased in the second implantation.Type: ApplicationFiled: April 20, 2015Publication date: March 30, 2017Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Yuki HORIUCHI, Satoru KAMEYAMA
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Patent number: 9577081Abstract: A semiconductor device includes a semiconductor substrate that includes an IGBT region. A first lifetime control layer extending along a planar direction of the semiconductor substrate is provided in a range in a drift region that is closer to the rear surface than an intermediate portion of the semiconductor substrate in a thickness direction. A crystal defect density in the first lifetime control layer is higher than any of a crystal defect density in a region adjacent to the first lifetime control layer on the rear surface side and a crystal defect density in a region adjacent to the first lifetime control layer on a front surface side. A crystal defect density in a region between the first lifetime control layer and the rear surface is lower than a crystal defect density in a region between the first lifetime control layer and the front surface.Type: GrantFiled: January 26, 2016Date of Patent: February 21, 2017Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Satoru Kameyama, Shinya Iwasaki
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Patent number: 9570353Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming of an interlayer insulating film on a semiconductor substrate; etching the interlayer insulating film to form a contact hole and an alignment hole wider than the contact hole; depositing a first metal layer having a thickness thicker than a half of the width of the contact hole and thinner than a half of the width of the alignment hole; etching the first metal layer so that a bottom surface of the alignment hole are exposed and the first metal layer remains covering a bottom surface of the contact hole; treating the semiconductor substrate based on the position of the alignment hole; and cutting a part of the semiconductor substrate including the alignment hole to divide a semiconductor device having the contact hole from the semiconductor substrate.Type: GrantFiled: July 14, 2016Date of Patent: February 14, 2017Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Satoru Kameyama, Shinya Iwasaki, Yuki Yakushigawa
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Publication number: 20170033099Abstract: A semiconductor device includes an interlayer insulating film in which first contact holes and second contact holes are provided. Each of the second contact holes has a width narrower than a width of the corresponding first contact hole. A contact plug is located in the corresponding second contact hole. An upper electrode layer is arranged on an upper surface of the interlayer insulating film, upper surfaces of the contact plugs, and inner surfaces of the first contact holes. The protective insulating film covers an upper surface of the external field. An end portion extending along a direction intersecting with the plurality of trenches of the protective insulating film extends through a range located above the plurality of the second contact holes. A pillar region is in contact with the upper electrode layer in the first contact hole.Type: ApplicationFiled: June 6, 2016Publication date: February 2, 2017Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Shinya IWASAKI, Satoru KAMEYAMA, Yuki YAKUSHIGAWA
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Publication number: 20170025310Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming of an interlayer insulating film on a semiconductor substrate; etching the interlayer insulating film to form a contact hole and an alignment hole wider than the contact hole; depositing a first metal layer having a thickness thicker than a half of the width of the contact hole and thinner than a half of the width of the alignment hole; etching the first metal layer so that a bottom surface of the alignment hole are exposed and the first metal layer remains covering a bottom surface of the contact hole; treating the semiconductor substrate based on the position of the alignment hole; and cutting a part of the semiconductor substrate including the alignment hole to divide a semiconductor device having the contact hole from the semiconductor substrate.Type: ApplicationFiled: July 14, 2016Publication date: January 26, 2017Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Satoru KAMEYAMA, Shinya IWASAKI, Yuki YAKUSHIGAWA
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Publication number: 20170012039Abstract: A semiconductor device, in which, in a density distribution of first conductivity type impurities in the first conductivity type region measured along a thickness direction of the semiconductor substrate, a local maximum value N1, a local minimum value N2, a local maximum value N3, and a density N4 are formed in this order from front surface side, a relationship of N1>N3>N2>N4 is satisfied, a relationship of N3/10>N2 is satisfied, and a distance “a” from the surface to the depth having the local maximum value N1 is larger than twice a distance “b” from the depth having the local maximum value N1 to the depth having the local minimum N2.Type: ApplicationFiled: September 8, 2014Publication date: January 12, 2017Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Satoru KAMEYAMA, Shinya IWASAKI, Yuki HORIUCHI, Shuhei OKI
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Publication number: 20160372584Abstract: A semiconductor device includes a main IGBT region in which an IGBT is provided, a main diode region in which a diode is provided, a sense IGBT region in which an IGBT is provided, and a sense diode region in which a diode is provided. A clearance between the body region and the anode region is longer than a product of electron mobility and electron lifetime in the n-type region between the body region and the anode region. A clearance between an end of the collector region on a sense diode region side and the body region is longer than a product of electron mobility and electron lifetime in the n-type region between the end and the body region.Type: ApplicationFiled: September 8, 2014Publication date: December 22, 2016Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Keisuke KIMURA, Satoru KAMEYAMA
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Publication number: 20160351688Abstract: A method of manufacturing an insulated gate switching device includes: forming a trench in a front surface of a semiconductor substrate; forming a gate insulating film in the trench; depositing an electrode layer made of semiconductor in the trench and on the front surface after forming the gate insulating film; polishing the electrode layer so as to remove a portion of the electrode layer on the front surface and expose an underlayer of the removed portion of the electrode layer; forming a cap insulating film in a surface layer of a portion of the electrode layer in the trench by heating the semiconductor substrate after exposing the underlayer; and implanting impurities from above the front surface into a range extending across the portion of the electrode layer in the trench and the semiconductor substrate.Type: ApplicationFiled: May 18, 2016Publication date: December 1, 2016Inventors: Satoru Kameyama, Shinya Iwasaki, Seiji Arakawa
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Publication number: 20160352211Abstract: A semiconductor module is provided with a high potential wiring, an output wiring, a low potential wiring, an upper arm switching device, an upper arm diode, a lower arm switching device, and a lower arm diode. A ratio of steady loss to switching loss of the upper arm switching device is configured to be smaller than a ratio of steady loss to switching loss of the lower arm switching device. Further, a ratio of steady loss to switching loss of the upper arm diode is configured to be smaller than a ratio of steady loss to switching loss of the lower arm diode.Type: ApplicationFiled: January 7, 2015Publication date: December 1, 2016Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Satoru KAMEYAMA
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Publication number: 20160329323Abstract: A small semiconductor device having a diode forward voltage less likely to change due to a gate potential is provided. An anode and an upper IGBT structure (emitter and body) are provided in a range in the substrate exposed at the upper surface. A trench, a gate insulating film, and a gate electrode extend along a border of the anode and the upper IGBT structure. Cathode and collector are provided in a range in the substrate exposed at the lower surface. A drift is provided between an upper structure and a lower structure. A crystal defect region extends across the drift above the cathode and the drift above the collector. When a thickness of the substrate is defined as x [?m] and a width of a portion of the crystal defect region that protrudes above the cathode is defined as y [?m], y?0.007x2?1.09x+126 is satisfied.Type: ApplicationFiled: July 17, 2014Publication date: November 10, 2016Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Shinya Iwasaki, Satoru Kameyama
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Publication number: 20160315140Abstract: An IGBT region includes a collector layer, a first drift layer, a first body layer, an emitter layer, and a trench gate reaching the first drift layer through the first body layer from a front surface side of a semiconductor substrate. A diode region includes a cathode layer, a second drift layer, and a second body layer. A lifetime control region which includes a peak of a crystal defect density is provided in the first drift layer and the second drift layer that are located between a depth of a lower end of the trench gate and surfaces of the first drift layer and the second drift layer. A silicon nitride film is further provided above the trench gate on the front surface side of the semiconductor substrate.Type: ApplicationFiled: November 19, 2014Publication date: October 27, 2016Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Shinya IWASAKI, Satoru KAMEYAMA
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Publication number: 20160284693Abstract: A semiconductor device including a semiconductor substrate in which a diode region and an IGBT region are formed is provided. In the semiconductor device, the diode region includes a second conductivity type cathode layer. An impurity concentration of second conductivity type impurities of the cathode layer is distributed in a curve pattern having at least two peaks, and the impurity concentration of the second conductivity type impurities is higher than that of first conductivity type impurities at all depths of the cathode layer.Type: ApplicationFiled: June 8, 2016Publication date: September 29, 2016Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Satoru KAMEYAMA
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Publication number: 20160254374Abstract: A semiconductor device includes a semiconductor substrate that includes an IGBT region. A first lifetime control layer extending along a planar direction of the semiconductor substrate is provided in a range in a drift region that is closer to the rear surface than an intermediate portion of the semiconductor substrate in a thickness direction. A crystal defect density in the first lifetime control layer is higher than any of a crystal defect density in a region adjacent to the first lifetime control layer on the rear surface side and a crystal defect density in a region adjacent to the first lifetime control layer on a front surface side. A crystal defect density in a region between the first lifetime control layer and the rear surface is lower than a crystal defect density in a region between the first lifetime control layer and the front surface.Type: ApplicationFiled: January 26, 2016Publication date: September 1, 2016Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Satoru KAMEYAMA, Shinya IWASAKI
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Publication number: 20160247808Abstract: Provided is a technology for further reducing a loss in a semiconductor device including a semiconductor substrate in which an IGBT region and a diode region are provided. This semiconductor device includes a semiconductor substrate in which at least one IGBT region and at least one diode region are provided. The IGBT region and the diode region are adjacent to each other in a predetermined direction in a plan view of the semiconductor substrate. In the plan view of the semiconductor substrate, a first boundary plane where the collector region and the cathode region are adjacent is shifted from a second boundary plane where the IGBT region and the diode region are adjacent on the front surface side of the semiconductor substrate either in a direction from the cathode region toward the collector region or in a direction from the collector region toward the cathode region.Type: ApplicationFiled: November 5, 2013Publication date: August 25, 2016Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Yuki HORIUCHI, Satoru KAMEYAMA
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Patent number: 9397206Abstract: A semiconductor device including a semiconductor substrate in which a diode region and an IGBT region are formed is provided. In the semiconductor device, the diode region includes a second conductivity type cathode layer. An impurity concentration of second conductivity type impurities of the cathode layer is distributed in a curve pattern having at least two peaks, and the impurity concentration of the second conductivity type impurities is higher than that of first conductivity type impurities at all depths of the cathode layer.Type: GrantFiled: November 9, 2011Date of Patent: July 19, 2016Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Satoru Kameyama
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Patent number: 9379225Abstract: A semiconductor device in which an IGBT region and a diode region are formed on one semiconductor substrate is disclosed. The IGBT region includes: a body layer of a first conductivity type that is formed on a front surface of the semiconductor substrate; a body contact layer of the first conductivity type that is partially formed on a front surface of the body layer and has a higher impurity concentration of the first conductivity type than the body layer; an emitter layer of a second conductivity type that is partially formed on the front surface of the body layer; a drift layer; a collector layer; and a gate electrode. In the semiconductor device, a part of the body contact layer placed at a long distance from the diode region is made larger than a part of the body contact layer placed at a short distance from the diode region.Type: GrantFiled: February 13, 2013Date of Patent: June 28, 2016Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Keisuke Kimura, Satoru Kameyama, Masaki Koyama, Sachiko Aoi
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Publication number: 20160163647Abstract: A semiconductor device comprises a conductive layer, a first insulating film, a barrier metal, a contact electrode, and a surface electrode. The first insulating film is located on the conductive layer and comprises a contact hole reaching the conductive layer. At least a surface part of the first insulating film is a BPSG film. The barrier metal covers an inner surface of the contact hole. The contact electrode is located in the contact hole and on the barrier metal. The surface electrode is located on the BPSG film and the contact electrode. The barrier metal is not interposed between the BPSG film and the surface electrode so that the surface electrode is directly in contact with the BPSG film. At least a part of the surface electrode is a bonding pad.Type: ApplicationFiled: November 20, 2015Publication date: June 9, 2016Inventors: Shinya IWASAKI, Satoru KAMEYAMA
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Patent number: 9312372Abstract: A semiconductor device in which an element region including at least an IGBT region is formed on a semiconductor substrate is presented. The IGBT region including: a collector layer; a drift layer; a body layer; a gate electrode placed inside a trench extending from the front surface of the semiconductor substrate to the drift layer; an emitter layer; and a contact layer having a higher impurity concentration than the body layer. In the semiconductor device, assuming that an x direction is a direction in which the trench extends along the front surface of the semiconductor substrate and that a y direction is a direction orthogonal to the x direction along the front surface of the semiconductor substrate, a distance from the contact layer to the emitter layer in the x direction is larger than a distance from the contact layer to the trench in the y direction.Type: GrantFiled: February 13, 2013Date of Patent: April 12, 2016Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Keisuke Kimura, Satoru Kameyama
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Publication number: 20160005844Abstract: A semiconductor device in which an IGBT region and a diode region are formed on one semiconductor substrate is disclosed. The IGBT region includes: a body layer of a first conductivity type that is formed on a front surface of the semiconductor substrate; a body contact layer of the first conductivity type that is partially formed on a front surface of the body layer and has a higher impurity concentration of the first conductivity type than the body layer; an emitter layer of a second conductivity type that is partially formed on the front surface of the body layer; a drift layer; a collector layer; and a gate electrode. In the semiconductor device, a part of the body contact layer placed at a long distance from the diode region is made larger than a part of the body contact layer placed at a short distance from the diode region.Type: ApplicationFiled: February 13, 2013Publication date: January 7, 2016Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Keisuke KIMURA, Satoru KAMEYAMA, Masaki KOYAMA, Sachiko AOI