Patents by Inventor Satoshi Kawasaki
Satoshi Kawasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110058426Abstract: A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.Type: ApplicationFiled: November 11, 2010Publication date: March 10, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yoshihiko KUSAKABE, Kenichi Oto, Satoshi Kawasaki
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Patent number: 7859909Abstract: A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.Type: GrantFiled: August 24, 2009Date of Patent: December 28, 2010Assignee: Renesas Electronics CorporationInventors: Yoshihiko Kusakabe, Kenichi Oto, Satoshi Kawasaki
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Publication number: 20100206444Abstract: There are provided a rubber composition for tire including a rubber component containing at least one selected from the group consisting of natural rubber, epoxidized natural rubber and deproteinized natural rubber; silica; and a silane compound represented by the following general formula (1) (X)n—Si—Y(4-n)??(1) (wherein X represents a methoxy group or an ethoxy group, Y represents a phenyl group or a straight-chain or branched alkyl group, and n represents an integer of 1 to 3), and a pneumatic tire using the same. The rubber composition for tire can be suitably used for manufacturing bead apex rubber and base tread rubber of tire.Type: ApplicationFiled: March 7, 2008Publication date: August 19, 2010Inventor: Satoshi Kawasaki
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Publication number: 20100113663Abstract: The present invention aims to produce a rubber composition for a base tread, which suppresses reversion and achieves excellent mechanical strength, fuel economy and processability, and a tire using the rubber composition, with high efficiency to provide them to customers at low prices. The present invention relates to a rubber composition for a base tread, containing: a rubber component; and a mixture of a zinc salt of an aliphatic carboxylic acid and a zinc salt of an aromatic carboxylic acid, wherein the rubber component contains natural rubber and butadiene rubber, the butadiene rubber content being 10 to 90% by mass per 100% by mass of the rubber component, and the mixture of a zinc salt of an aliphatic carboxylic acid and a zinc salt of an aromatic carboxylic acid is contained in an amount of 1 to 10 parts by mass per 100 parts by mass of the rubber component.Type: ApplicationFiled: September 9, 2009Publication date: May 6, 2010Inventors: Satoshi KAWASAKI, Takayuki Hattori
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Publication number: 20090310410Abstract: A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.Type: ApplicationFiled: August 24, 2009Publication date: December 17, 2009Applicant: Renesas Technology CorporationInventors: Yoshihiko Kusakabe, Kenichi Oto, Satoshi Kawasaki
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Patent number: 7596033Abstract: A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.Type: GrantFiled: July 7, 2008Date of Patent: September 29, 2009Assignee: Renesas Technology Corp.Inventors: Yoshihiko Kusakabe, Kenichi Oto, Satoshi Kawasaki
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Publication number: 20080273396Abstract: A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.Type: ApplicationFiled: July 7, 2008Publication date: November 6, 2008Applicant: RENESAS TECHNOLOGY CORP.Inventors: Yoshihiko Kusakabe, Kenichi Oto, Satoshi Kawasaki
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Publication number: 20080191476Abstract: A joint for a measuring device includes a fluid introduction sleeve to which a body of a measuring device is mounted, a gasket holding member mounted to the fluid introduction sleeve so as to project over a front end of the fluid introduction sleeve, and a gasket having an annular shape and held by the gasket holding member. The gasket is held to the gasket holding member by plastically deforming the gasket in a radially inward direction thereof.Type: ApplicationFiled: February 14, 2008Publication date: August 14, 2008Applicant: NAGANO KEIKI CO., LTD.Inventors: Satoshi KAWASAKI, Yasutaka IDE, Kunihiro YAMAURA
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Patent number: 7411834Abstract: A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.Type: GrantFiled: February 2, 2007Date of Patent: August 12, 2008Assignee: Renesas Technology Corp.Inventors: Yoshihiko Kusakabe, Kenichi Oto, Satoshi Kawasaki
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Patent number: 7365578Abstract: In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of ?9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.Type: GrantFiled: July 3, 2007Date of Patent: April 29, 2008Assignee: Renesas Technology Corp.Inventors: Minoru Senda, Kiyohiro Furutani, Taku Ogura, Shigehiro Kuge, Satoshi Kawasaki, Tadaaki Yamauchi
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Publication number: 20070285146Abstract: In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of ?9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.Type: ApplicationFiled: July 3, 2007Publication date: December 13, 2007Applicant: RENESAS TECHNOLOGY CORP.Inventors: Minoru Senda, Kiyohiro Furutani, Taku Ogura, Shigehiro Kuge, Satoshi Kawasaki, Tadaaki Yamauchi
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Patent number: 7268612Abstract: In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of ?9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.Type: GrantFiled: January 30, 2007Date of Patent: September 11, 2007Assignee: Renesas Technology Corp.Inventors: Minoru Senda, Kiyohiro Furutani, Taku Ogura, Shigehiro Kuge, Satoshi Kawasaki, Tadaaki Yamauchi
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Publication number: 20070183213Abstract: A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.Type: ApplicationFiled: February 2, 2007Publication date: August 9, 2007Inventors: Yoshihiko Kusakabe, Kenichi Oto, Satoshi Kawasaki
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Publication number: 20070120592Abstract: In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of ?9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.Type: ApplicationFiled: January 30, 2007Publication date: May 31, 2007Applicant: Renesas Technology Corp.Inventors: Minoru Senda, Kiyohiro Furutani, Taku Ogura, Shigehiro Kuge, Satoshi Kawasaki, Tadaaki Yamauchi
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Patent number: 7180362Abstract: In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of ?9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.Type: GrantFiled: September 15, 2004Date of Patent: February 20, 2007Assignee: Renesas Technology Corp.Inventors: Minoru Senda, Kiyohiro Furutani, Taku Ogura, Shigehiro Kuge, Satoshi Kawasaki, Tadaaki Yamauchi
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Patent number: 7144039Abstract: A vehicle front body structure includes a pair of front side frames each of which has, at a rear portion thereof, an easily deformable portion that is easily deformable during a collision, a support frame for mounting a unit box thereon, which has a pair of rear legs that are fixed to the easily deformable portions of the pair of front side frames, and a pair of front legs that are fixed to portions of the pair of front side frames, the portions being located in the front as viewed from the easily deformable portions. Displacement allowing spaces for allowing displacement of the unit box during a collision are provided near side portions of the unit box adjacent to the rear legs.Type: GrantFiled: November 7, 2003Date of Patent: December 5, 2006Assignee: Honda Motor Co., Ltd.Inventors: Satoshi Kawasaki, Tomohiro Fukazu, Hiroyuki Hattori
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Patent number: 7137466Abstract: An arrangement structure for a fuel cell system in a vehicle including a fuel cell box which holds a fuel cell, a sub-frame which holds a fuel gas tank, and a fuel gas dilution box. The sub-frame is placed so as to be aligned with the fuel cell box, and the fuel gas dilution box is disposed between the fuel cell and the sub-frame.Type: GrantFiled: November 6, 2003Date of Patent: November 21, 2006Assignee: Honda Motor Co., Ltd.Inventors: Satoshi Kawasaki, Katsumi Saito, Kazunori Fukuma
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Patent number: 7086492Abstract: A fuel cell vehicle driven by generated electric power of a fuel cell comprises a fuel cell box disposed underneath a floor for storing therein the fuel call, G sensors for detecting a deformation of a vehicle body sideward of the fuel cell box, and a shut-off valve for closing a supply side piping of a hydrogen gas supplied to the fuel cell when a predetermined amount of deformation or the vehicle body is detected by the G sensors.Type: GrantFiled: August 22, 2003Date of Patent: August 8, 2006Assignee: Honda Giken Kogyo Kabushiki KaishaInventors: Satoshi Kawasaki, Tohru Ono, Yukio Hiruta
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Patent number: 7040432Abstract: A wire and pipe-laying structure for a fuel cell vehicle including a rear frame which is disposed at a back of the fuel cell vehicle and extends in a longitudinal direction of the fuel cell vehicle; a side sill which is disposed at a side of the fuel cell vehicle; and a floor frame which is disposed inside the side sill and extends in a longitudinal direction of the fuel cell vehicle. The floor frame together with the side sill are connected to a front end of the rear frame so as to form a Y-shaped frame having a crotch portion. A fuel pipe or a high-voltage wiring is disposed so as to pass through the crotch portion of the Y-shaped frame, and the fuel pipe or high-voltage wiring connects a fuel tank for fuel gas or a storage device to a fuel cell box.Type: GrantFiled: November 6, 2003Date of Patent: May 9, 2006Assignee: Honda Motor Co., Ltd.Inventors: Satoshi Kawasaki, Takanori Mouri
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Patent number: 7030437Abstract: A semiconductor device includes two sense amplifiers provided on a semiconductor substrate. Each of two sense amplifiers is formed of a pair of transistors. Two transistors are separated from each other by an element-isolating insulating portion provided on the semiconductor substrate. Therefore unlike the conventional, two transistors do not share the source region with each other, resulting in a semiconductor device with an improved sensitivity of a sense amplifier.Type: GrantFiled: May 22, 2003Date of Patent: April 18, 2006Assignee: Renesas Technology Corp.Inventors: Satoshi Yodogawa, Satoshi Kawasaki, Takeshi Hamamoto