Patents by Inventor Satoshi Kazama
Satoshi Kazama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11580023Abstract: An information processing apparatus including: a first management data storing region that stores a plurality of first links being provided one for each of multiple calculating cores and representing an order of migration of pages of a page group allocated to the calculating core among a plurality of the pages; a second management data storing region that stores a second link being provided for an operating system and managing a plurality of pages selected in accordance with the order of migration among the page group of the plurality of first links as a group of candidate pages to be migrated to the second memory; and a migration processor that migrates data of a page selected from the group of the second link from the first memory to the second memory. With this configuration, occurrence of a spinlock is reduced, so that the load on processor is reduced.Type: GrantFiled: March 2, 2021Date of Patent: February 14, 2023Assignee: FUJITSU LIMITEDInventors: Satoshi Kazama, Shinya Kuwamura
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Patent number: 11301133Abstract: An analysis device configured to be connected to an information processing apparatus configured to mount a first memory and a low-speed second memory, the low-speed second memory being cheaper and having lower performance than the first memory and being used for memory capacity expansion, the analysis device being configured to perform program instructions including: causing the information processing apparatus to execute a plurality of types of performance evaluation application programs and acquire memory performance characteristic information regarding each performance evaluation application program from the information processing apparatus; determining a recommended memory configuration according to the performance evaluation application program corresponding to the application to be evaluated program among the plurality of types of performance evaluation application programs by using a collection result of the memory performance characteristic information; and outputting recommended memory configurationType: GrantFiled: October 16, 2020Date of Patent: April 12, 2022Assignee: FUJITSU LIMITEDInventors: Hiroyoshi Kodama, Satoshi Kazama
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Publication number: 20210286725Abstract: An information processing apparatus including: a first management data storing region that stores a plurality of first links being provided one for each of multiple calculating cores and representing an order of migration of pages of a page group allocated to the calculating core among a plurality of the pages; a second management data storing region that stores a second link being provided for an operating system and managing a plurality of pages selected in accordance with the order of migration among the page group of the plurality of first links as a group of candidate pages to be migrated to the second memory; and a migration processor that migrates data of a page selected from the group of the second link from the first memory to the second memory. With this configuration, occurrence of a spinlock is reduced, so that the load on processor is reduced.Type: ApplicationFiled: March 2, 2021Publication date: September 16, 2021Applicant: FUJITSU LIMITEDInventors: Satoshi KAZAMA, Shinya KUWAMURA
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Publication number: 20210224153Abstract: An information processing apparatus includes: a nonvolatile memory having a plurality of unit storage regions; and a processor coupled to the nonvolatile memory, the processor being configured to: write a check bit, which is a fixed value, at each of a plurality of positions in a single unit storage region; write data to be written to a storage region other than the plurality of positions in the single unit storage region when data is written to the single unit storage region of the plurality of unit storage regions; read the check bits from the single unit storage region; and determine an occurrence status of data corruption in the single unit storage region on the basis of a bit value of each of the read check bits.Type: ApplicationFiled: January 5, 2021Publication date: July 22, 2021Applicant: FUJITSU LIMITEDInventor: Satoshi Kazama
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Patent number: 11038981Abstract: A server configured to accept a request from a client terminal includes a storage configured to store a description file including a script to cause the client terminal to perform a confirmation process to confirm availability of access to a predetermined host server with a predetermined port number, and a unit configured to transmit the description file stored in the storage to the client terminal based on the request.Type: GrantFiled: August 3, 2016Date of Patent: June 15, 2021Assignee: SATO HOLDINGS KABUSHIKI KAISHAInventor: Satoshi Kazama
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Publication number: 20210173565Abstract: An analysis device configured to be connected to an information processing apparatus configured to mount a first memory and a low-speed second memory, the low-speed second memory being cheaper and having lower performance than the first memory and being used for memory capacity expansion, the analysis device being configured to perform program instructions including: causing the information processing apparatus to execute a plurality of types of performance evaluation application programs and acquire memory performance characteristic information regarding each performance evaluation application program from the information processing apparatus; determining a recommended memory configuration according to the performance evaluation application program corresponding to the application to be evaluated program among the plurality of types of performance evaluation application programs by using a collection result of the memory performance characteristic information; and outputting recommended memory configurationType: ApplicationFiled: October 16, 2020Publication date: June 10, 2021Applicant: FUJITSU LIMITEDInventors: Hiroyoshi Kodama, Satoshi Kazama
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Patent number: 11029878Abstract: An information processing system includes a first processor, a second processor, a first buffer circuit, a second buffer circuit, and a first memory, wherein the first processor is configured to generate a first read command specifying a first data stored in a first address area of the first memory, the second processor is configured to, based on the first read command, generate a second read command specifying a second data stored in a second address area of the first memory, the first buffer circuit is configured to store the first read command, the second buffer circuit is configured to store the second read command, the second processor is configured to execute the first read command stored in the first buffer circuit, and the second processor is configured to execute the second read command stored in the second buffer circuit when the first buffer circuit is in an empty state.Type: GrantFiled: May 31, 2017Date of Patent: June 8, 2021Assignee: FUJITSU LIMITEDInventor: Satoshi Kazama
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Patent number: 11029892Abstract: A memory control apparatus includes a first memory, a second memory, a third memory, and a processor configured to add, to management information, first identification information and information indicating a position where first data is stored when the first data is stored in the first memory, add, to the management information, the first identification information and information indicating a position where second data is stored when the second data is stored in the second memory, add, to the management information, second identification information and information indicating a position where third data is stored when the third data is stored in the third memory, determine which one of the first identification information and the second identification information is associated with fourth data, and perform retrieval of the fourth data from the first memory or the second memory in accordance with information indicating a position where the fourth data is stored.Type: GrantFiled: April 26, 2019Date of Patent: June 8, 2021Assignee: FUJITSU LIMITEDInventors: Satoshi Kazama, Shinya Kuwamura
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Patent number: 11003577Abstract: An information processing apparatus includes: a first memory including a semiconductor device memory; a second memory including a cache memory, the second memory being configured to temporarily store data to be written in the semiconductor device memory; and a processor configured to execute a writing-back process that includes providing a notification regarding completion of writing of the data before the data stored in the second memory is written in the first memory, execute an alternative writing process that includes writing the data at a second physical address in the first memory when writing of the data at a first physical address in the first memory is failed, and execute an access process that includes accessing the data written at the second physical address based on address management information, the address management information indicating a correspondence between the first physical address and the second physical address.Type: GrantFiled: June 19, 2019Date of Patent: May 11, 2021Assignee: FUJITSU LIMITEDInventor: Satoshi Kazama
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Patent number: 10860225Abstract: An information processing apparatus includes a memory and a processor and accesses a first storage device and a second storage device wherein an access speed of the second storage device is higher than an access speed of the first storage device. The memory stores information relating to a request in a request from the information processing apparatus to the second storage device. The processor, which is connected to the memory, determines a load on the second storage device based on the information relating to the request.Type: GrantFiled: March 19, 2018Date of Patent: December 8, 2020Assignee: FUJITSU LIMITEDInventors: Satoshi Kazama, Shinya Kuwamura, Eiji Yoshida, Junji Ogawa
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Publication number: 20200233604Abstract: An information processing apparatus includes a non-volatile storage device; a memory; and a processor coupled to the memory and configured to execute a scrubbing processing, the scrubbing processing including: reading out data from the storage device, determining whether a re-write of the data is required according to a result of reading out the data, and re-writing the data which has been read out at a same position in the storage device consecutively multiple times when it is determined that the re-write is required.Type: ApplicationFiled: January 10, 2020Publication date: July 23, 2020Applicant: FUJITSU LIMITEDInventor: Satoshi Kazama
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Publication number: 20190347048Abstract: A memory control apparatus includes a first memory, a second memory, a third memory, and a processor configured to add, to management information, first identification information and information indicating a position where first data is stored when the first data is stored in the first memory, add, to the management information, the first identification information and information indicating a position where second data is stored when the second data is stored in the second memory, add, to the management information, second identification information and information indicating a position where third data is stored when the third data is stored in the third memory, determine which one of the first identification information and the second identification information is associated with fourth data, and perform retrieval of the fourth data from the first memory or the second memory in accordance with information indicating a position where the fourth data is stored.Type: ApplicationFiled: April 26, 2019Publication date: November 14, 2019Applicant: FUJITSU LIMITEDInventors: Satoshi Kazama, Shinya KUWAMURA
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Publication number: 20190303287Abstract: An information processing apparatus includes: a first memory including a semiconductor device memory; a second memory including a cache memory, the second memory being configured to temporarily store data to be written in the semiconductor device memory; and a processor configured to execute a writing-back process that includes providing a notification regarding completion of writing of the data before the data stored in the second memory is written in the first memory, execute an alternative writing process that includes writing the data at a second physical address in the first memory when writing of the data at a first physical address in the first memory is failed, and execute an access process that includes accessing the data written at the second physical address based on address management information, the address management information indicating a correspondence between the first physical address and the second physical address.Type: ApplicationFiled: June 19, 2019Publication date: October 3, 2019Applicant: FUJITSU LIMITEDInventor: Satoshi Kazama
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Patent number: 10268388Abstract: An access control method includes: determining a number of a plurality of commands to be continuously transferred; transferring to a storage device, a transfer preparation completion command indicating that preparation for transfer of the plurality of commands is completed, when it is determined that the number is greater than or equal to a threshold value; transferring, in sequence, to the storage device, the plurality of commands when it is determined that the number is less than the threshold value; when a command transferred from the host device is the transfer preparation completion command, issuing a direct memory access request to the host device based on the transfer preparation completion command and receiving the plurality of commands transferred from the host device by a direct memory access method based on the direct memory access request; and accessing the storage, based on each of the plurality of commands received.Type: GrantFiled: January 6, 2017Date of Patent: April 23, 2019Assignee: FUJITSU LIMITEDInventor: Satoshi Kazama
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Patent number: 10101946Abstract: A method of reading data from a first memory device includes generating a first read command based on a first request which requests to generate the first read command for first data stored in a first address region of the first memory device, generating a second read command for second data stored in a second address region of the first memory device, generating a third read command based on a second request which requests to generate the third read command for third data stored in a third address region of the first memory device, executing the first read command and the third read command to read the first data and the third data, respectively, from the first memory device, and after the executing the first read command and the third read command, executing the second read command to read the second data from the first memory device.Type: GrantFiled: July 6, 2016Date of Patent: October 16, 2018Assignee: FUJITSU LIMITEDInventor: Satoshi Kazama
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Publication number: 20180285012Abstract: An information processing apparatus includes a memory and a processor and accesses a first storage device and a second storage device wherein an access speed of the second storage device is higher than an access speed of the first storage device. The memory stores information relating to a request in a request from the information processing apparatus to the second storage device. The processor, which is connected to the memory, determines a load on the second storage device based on the information relating to the request.Type: ApplicationFiled: March 19, 2018Publication date: October 4, 2018Applicant: FUJITSU LIMITEDInventors: Satoshi Kazama, Shinya KUWAMURA, Eiji Yoshida, JUNJI OGAWA
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Patent number: 9977602Abstract: The storage device includes multiple NAND devices each of which performs a process on the basis of a command; a command management unit that issues the command from a host to one of the NAND devices specified by the command and that sends an issue completion notification of the issued command to the host; and a state notifying unit that notifies, based on whether each of the NAND devices performs a predetermined process, the host whether each of the NAND devices is ready to accept the command. The host includes a NAND control unit that selects one of the NAND devices that is ready to accept the command based on the notification from the state notifying unit when the issue completion notification is received and sends, to the command management unit, a command to allow the selected one of the NAND devices to perform the process.Type: GrantFiled: May 7, 2014Date of Patent: May 22, 2018Assignee: FUJITSU LIMITEDInventor: Satoshi Kazama
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Publication number: 20180091622Abstract: A server configured to accept a request from a client terminal includes a storage configured to store a description file including a script to cause the client terminal to perform a confirmation process to confirm availability of access to a predetermined host server with a predetermined port number, and a unit configured to transmit the description file stored in the storage to the client terminal based on the request.Type: ApplicationFiled: August 3, 2016Publication date: March 29, 2018Applicant: SATO HOLDINGS KABUSHIKI KAISHAInventor: Satoshi KAZAMA
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Publication number: 20170371586Abstract: An information processing system includes a first processor, a second processor, a first buffer circuit, a second buffer circuit, and a first memory, wherein the first processor is configured to generate a first read command specifying a first data stored in a first address area of the first memory, the second processor is configured to, based on the first read command, generate a second read command specifying a second data stored in a second address area of the first memory, the first buffer circuit is configured to store the first read command, the second buffer circuit is configured to store the second read command, the second processor is configured to execute the first read command stored in the first buffer circuit, and the second processor is configured to execute the second read command stored in the second buffer circuit when the first buffer circuit is in an empty state.Type: ApplicationFiled: May 31, 2017Publication date: December 28, 2017Applicant: FUJITSU LIMITEDInventor: Satoshi Kazama
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Publication number: 20170206029Abstract: An access control method includes: determining a number of a plurality of commands to be continuously transferred; transferring to a storage device, a transfer preparation completion command indicating that preparation for transfer of the plurality of commands is completed, when it is determined that the number is greater than or equal to a threshold value; transferring, in sequence, to the storage device, the plurality of commands when it is determined that the number is less than the threshold value; when a command transferred from the host device is the transfer preparation completion command, issuing a direct memory access request to the host device based on the transfer preparation completion command and receiving the plurality of commands transferred from the host device by a direct memory access method based on the direct memory access request; and accessing the storage, based on each of the plurality of commands received.Type: ApplicationFiled: January 6, 2017Publication date: July 20, 2017Applicant: FUJITSU LIMITEDInventor: Satoshi Kazama