Abstract: A Local Dynamic Power Controller (LDPC) generates and deliver to a load a full swing voltage supply signal and a reduced swing voltage supply signal. Both the full and reduce voltage supply signals are generated from a single power supply. The full swing voltage supply signal is supplied when the load is in full operational mode whereas the reduce voltage supply signal is provided when the load is in a sleep mode. As a consequence, power dissipated in the load is reduced.

Abstract: Embodiments that decrease power consumption of interconnecting devices in integrated circuits are disclosed. Embodiments reduce power consumption in integrated circuits by generating full and reduced swing signals at an output of a driver module in response to a control signal during and deactivating one or more elements to conserve power after an input signal remains unchanged for a period of time. Another embodiment reduces power consumption in a circuit, the embodiment comprising a swing module coupled with a swing selector and an output controller. The swing module may generate full or low swing signals depending on the state of the swing selector. The output controller may increase the output impedance of the swing module after an input signal to the swing module remains unchanged for a quantity of time. Various apparatus embodiments include portable computing devices and cellular telephones.

Abstract: Methods and apparatuses to decrease power consumption and reduce leakage current of integrated circuits are disclosed. New leakage power saving techniques for various types of integrated circuits, including cache memory circuits, are discussed. Embodiments comprise methods and apparatuses to reduce power consumption in integrated circuits by using virtual voltage rails, or virtual power rails, to supply power to integrated circuit loads. The methods and apparatuses generally involve using one or two virtual power control devices to “head” and “foot”, or sandwich, the integrated circuit loads from firm power supply rails. In these method embodiments, one or more elements sense the voltage of the virtual power rails, or nodes, and make adjustments to control the voltage at certain “virtual” voltage potentials. While controlling the voltage in this manner, the virtual power control devices may serve to restrict unnecessary current flow through the integrated circuit loads.

Abstract: Methods and apparatuses to decrease power consumption and reduce leakage current of integrated circuits are disclosed. New leakage power saving techniques for various types of integrated circuits, including cache memory circuits, are discussed. Embodiments comprise methods and apparatuses to reduce power consumption in integrated circuits by using virtual voltage rails, or virtual power rails, to supply power to integrated circuit loads. The methods and apparatuses generally involve using one or two virtual power control devices to “head” and “foot”, or sandwich, the integrated circuit loads from firm power supply rails. In these method embodiments, one or more elements sense the voltage of the virtual power rails, or nodes, and make adjustments to control the voltage at certain “virtual” voltage potentials. While controlling the voltage in this manner, the virtual power control devices may serve to restrict unnecessary current flow through the integrated circuit loads.

Abstract: A Local Dynamic Power Controller (LDPC) generates and deliver to a load a full swing voltage supply signal and a reduced swing voltage supply signal. Both the full and reduce voltage supply signals are generated from a single power supply. The full swing voltage supply signal is supplied when the load is in full operational mode whereas the reduce voltage supply signal is provided when the load is in a sleep mode. As a consequence, power dissipated in the load is reduced.

Abstract: A Local Dynamic Power Controller (LDPC) generates and deliver to a load a full swing voltage supply signal and a reduced swing voltage supply signal. Both the full and reduce voltage supply signals are generated from a single power supply. The full swing voltage supply signal is supplied when the load is in full operational mode whereas the reduce voltage supply signal is provided when the load is in a sleep mode. As a consequence, power dissipated in the load is reduced.

Abstract: Methods and apparatuses to decrease power consumption of interconnecting devices in integrated circuits are disclosed. Embodiments comprise a method to reduce power consumption in integrated circuits by generating full and reduced swing signals at an output of a driver module in response to a control signal during and deactivating one or more elements to conserve power after an input signal remains unchanged for a period of time. Another embodiment comprises an apparatus to reduce power consumption in a circuit, the embodiment comprising a swing module coupled with a swing selector and an output controller. The swing module may generate full or low swing signals depending on the state of the swing selector. The output controller may increase the output impedance of the swing module after an input signal to the swing module remains unchanged for a quantity of time. Various apparatus embodiments include portable computing devices and cellular telephones.

Abstract: A Local Dynamic Power Controller (LDPC) generates and deliver to a load a full swing voltage supply signal and a reduced swing voltage supply signal. Both the full and reduce voltage supply signals are generated from a single power supply. The full swing voltage supply signal is supplied when the load is in full operational mode whereas the reduce voltage supply signal is provided when the load is in a sleep mode. As a consequence, power dissipated in the load is reduced.

Abstract: A Local Dynamic Power Controller (LDPC) generates and deliver to a load a full swing voltage supply signal and a reduced swing voltage supply signal. Both the full and reduce voltage supply signals are generated from a single power supply. The full swing voltage supply signal is supplied when the load is in full operational mode whereas the reduce voltage supply signal is provided when the load is in a sleep mode. As a consequence, power dissipated in the load is reduced.

Abstract: The present invention allows for the simultaneous transmission of two digital signals from one integrated circuit to another. The two digital signals are encoded utilizing a voltage divider circuit and are then transmitted by one transmission line to the second integrated circuit chip. The second integrated circuit chip decodes the first digital signal and then utilizes this decoded digital signal to further decode the second digital signal.

Abstract: A repeater circuit (10) includes a decoder arrangement (34) and an encoder arrangement (33). The decoder arrangement (34) is connected to an input transmission line to receive an input encoded signal comprising a signal at one of four encoded voltage levels. Each of the four possible encoded voltage levels represents a different combination of first and second digital data signals. The decoder arrangement (34) decodes the input encoded signal to produce the first and second data signals. These first and second data signals then serve as inputs to the encoder (33) which encodes the signals into an output encoded signal. The output encoded signal comprises a signal similar to the input encoded signal but restored to account for parasitic resistance associated with the input transmission line (21).

Abstract: Circuit and method aspects are provided for voltage level translation circuit for an output driver. In a circuit aspect, a circuit includes an input mechanism for receiving an internal data signal of a first predetermined voltage range, at least two stacked transistors coupled to the input mechanism, and a bias generator coupled to the input mechanism and the at least two stacked transistors, the bias generator ensuring that the at least two stacked transistors operate below a predetermined maximum device voltage. The circuit further includes an output mechanism coupled to the at least two stacked transistors, the output mechanism providing an external signal of a second predetermined voltage range.

Abstract: An output driver which maintains over voltage protection on individual circuit elements, providing either a level shifted logic high or a floating-state on its output. The output driver includes a latch driven by a set circuit and a reset circuit. The latch output drives an output stage which produces a level shifted logic high when the latch is set and a floating-state when the latch is reset. Minimal voltage is applied across individual circuit elements by supplying power in concurrent incremental voltage levels to the output driver.

Abstract: Circuit and method aspects for translating acceptable voltage levels from an external device to acceptable voltage levels of an internal device are provided. These aspects include coupling an input receiver between the external device and the internal device, the input receiver including a clamp device, and coupling a bias generator to the input receiver at the clamp device, wherein the bias generator ensures proper translation of a high level input signal from the external device by the input receiver. The bias generator further ensures that a predetermined maximum device voltage of the clamp device is not exceeded.

Abstract: The present invention allows for the simultaneous transmission of two digital signals from one integrated circuit to another. The two digital signals are encoded utilizing a voltage divider circuit and are then transmitted by one transmission line to the second integrated circuit chip. The second integrated circuit chip decodes the first digital signal and then utilizes this decoded digital signal to further decode the second digital signal.

Abstract: A driver circuit including of one or more fingers, or parallel driver circuits, senses for an overshoot or an undershoot condition of the signal transmitted onto a transmission line coupled to the driver circuit and compensates for such an overshoot or an undershoot by temporarily turning off the offending transition portion of the driver circuit, or finger portion. This is accomplished by turning off the transistor applying one of the two supply voltages coupled to the output transmission line. Effectively, the compensation circuitry within the driver circuit more closely matches the output impedance of the driver circuit to the impedance on the driven transmission line.

Abstract: The present invention allows for the simultaneous transmission of three digital signals from one integrated circuit to another. The three digital signals are encoded utilizing series resistors of predetermined values and are then transmitted by one transmission line to the second integrated circuit chip. The second integrated circuit chip decodes the first digital signal and then utilizes this decoded first digital signal to further decode the second digital signal, and then utilizes the decoded first and second digital signals to decode the third digital signal.

Abstract: The present invention facilitates communication of signals from circuitry implemented with a first CMOS technology requiring a first voltage level supply for operation to circuitry implemented with a second CMOS technology requiring a second voltage level supply for operation, wherein the first and second voltage level supplies are not equal. The present invention receives from the circuitry implemented with a first CMOS technology a signal which has a first voltage level that is not acceptable for input into the circuitry implemented with a second CMOS technology. This signal is converted to a second voltage level that is acceptable for input into the circuitry implemented with a second CMOS technology, and then transmitted to the circuitry implemented with a second CMOS technology requiring a second voltage level supply for operation.

Abstract: A CMOS driver/receiver pair is provided which includes a non-inverting buffer in the input path to a differential receiver circuit. The non-inverting buffer allows a plurality of different voltages, and corresponding voltage swings, to be possible. This allows the differential receiver to compare the input voltage received from the transmission line with the output from its associated driver. Therefore, the receiver is capable of determining the voltage level (and the corresponding logic level) input from the transmission at the same time its associated driver is outputting a logic signal to another driver/receiver pair, via the transmission line. A single voltage source is utilized to provide multiple positive voltages to the differential receivers, such that differences in voltage levels which correspond to different logical combinations of "1" and "0" can be determined by the receiver.

Abstract: The present invention facilitates communication of signals from circuitry implemented with a first CMOS technology requiring a first voltage level supply for operation to circuitry implemented with a second CMOS technology requiring a second voltage level supply for operation, wherein the first and second voltage level supplies are not equal. The present invention receives from the circuitry implemented with a first CMOS technology a signal which has a first voltage level that is not acceptable for input into the circuitry implemented with a second CMOS technology. This signal is converted to a second voltage level that is acceptable for input into the circuitry implemented with a second CMOS technology, and then transmitted to the circuitry implemented with a second CMOS technology requiring a second voltage level supply for operation.