Memory Device with Control Circuit for Regulating Power Supply Voltage
A Local Dynamic Power Controller (LDPC) generates and deliver to a load a full swing voltage supply signal and a reduced swing voltage supply signal. Both the full and reduce voltage supply signals are generated from a single power supply. The full swing voltage supply signal is supplied when the load is in full operational mode whereas the reduce voltage supply signal is provided when the load is in a sleep mode. As a consequence, power dissipated in the load is reduced.
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This is a divisional application which claims priority of Patent Application Ser. No. 11/331,618, filed Jan. 13, 2006.
BACKGROUND OF THE INVENTION1. Field of Invention
The present invention relates to semiconductor integrated circuits in general and in particular to control circuits and method used to reduce power consumption in said semiconductor integrated circuits.
2. Description of Background Art
Most, if not all, equipment or appliances used in the workplace and/or home includes some type of semiconductor integrated circuit component, sometimes called Very Large Scale Integrated (VLSI) circuits, packaged as a chip or module. Even though the circuits are integrated on a substrate, logically they can be partitioned into a number of well known subsystems or components which may include latch array, SRAM, inverters, etc. For optimum performance adequate power must be provided to the subsystems or components. The power is usually provided via a power supply.
One of the concerns is that the power should be utilized to perform useful work and not be dissipated within the subsystem. It has been determined that most of the power dissipated results from leakage current present when the subsystem is in a non-operational mode. Several prior art patents attempt to solve this problem. Examples of such patents include U.S. Pat. Nos. 6,794,914, 6,657,911, 6,380,798, 6,333,571, 6,329,874, 6,222,410, 6,097,113, and 6,034,563,
The prior art also provides other approaches to address this problem. The clock system, composed by flip-flops and clock distribution network, is one of the most power consuming sub-systems in a VLSI circuit. Many techniques have been proposed to reduce clock system dissipation. Among them, Clock-Gating technique used for disabling the clock in inactive portions of the chip is generally considered as a useful approach for power reduction. The Double Gating and NC2MOS techniques apply gating technique separately to the master and slave latch, where a 20% to 40% power reduction is achieved when input switching activity is at about 10%. Since the Clock-Gating is used with lower granularity level, so the area overhead is the major problem for this technique. Other approaches have focused on the dynamic Vt technique, Power-Gating and alternative power supply for the memory core circuits, such as SRAM cells. In order to reduce leakage power dissipation, dynamic Vt technique creates low and high threshold voltages for the transistors with the memory core by applying dynamic body bias through a Local Bias Generator (LBG). In general, this approach requires some additional power supply and circuitry. The Power-Gating technique can significantly reduce the leakage power when memory is in drowsy mode, but the circuit may not retain the data under certain conditions and process variations. The alternative power supply technique uses nMOS pass gates to switch power supply for a memory block in order to reduce leakage power when it is not operational. The major drawback of this approach is that it also requires additional power resources. Further teachings on these techniques are set forth in the following documents:
H. Kawaguchi and T. Sakurai, “A Reduced Clock Swing Flip-Flop (FCSFF) for 63% Power Reduction”, IEEE Journal of Solid-State Circuits, 34(3), March 1999, pp. 405-414.
A. G. M. Strollo, E. Napoli and D. DeCaro, “New Clock-Gating Techniques for Low-Power Flip-Flops”,
C. H. Kim and K. Roy, “Dynamic Vt SRAM: A Leakage tolerant Cache Memory for Low Voltage Microprocessors”, Int. Symp. Low Power Electronics and Design (ISLPED), August 2002, pp. 251-254.
J. W. Tschanz, S. G. Narendra, et al, “Dynamic Sleep Transistor and Body Bias for Active Leakage Power Control of Microprocessors”, IEEE Journal of Solid-State Circuits, 38(aa), November 2003, pp. 1838-1845.
M. Power, K. Roy et al., “Gated-Vdd: A Circuit Technique to Reduce Leakage in Cache Memories”, Int. Symp. Low Power Electronics and Design (ISLPED), July 2000, pp. 90-95.
A. Agarwal, H. Li and K. Roy, “A Single-Vt Low-Leakage Gated-Ground Cache for Deep Submicron”, IEEE Journal of Solid State Circuits, vol. 38, February 2003, pp. 319-328.
P. Elakkumanan, and A. Narasimhan et al., “NC-SRAM—A Low-Leakage Memory Circuit for Ultra Deep Submicron designs”, IEEE SOC conference proceedings, September 2003, p. 3-6.
In view of the above a more efficient apparatus and method to reduce leakage current in VLSI circuits and/or storage systems is required. The reduction of leakage current ultimately results in less power consumption in the VLSI circuit.
SUMMARY OF THE INVENTIONA circuit arrangement termed Local Dynamic Power Controller (LDPC) includes switching devices that cause full voltage swing between Vdd and Gnd of a power supply to be applied to the VLSI and/or storage system during active operational mode and a reduced voltage swing between Vd and Gd to be applied during non-operational mode.
The LPDC does not require additional power resources since the reduced voltage (Vd and Gd) is generated from the normal power supply voltage required to provide power to the VLSI circuit and/or storage system to which the LPDC is coupled.
When the LPDC is coupled to a memory system the combined system creates a virtual power supply that is robust under process variations and consequently retains data stored in the memory system. Based upon simulation results it has been determined the LPDC technique results in approximately 80% leakage current reduction and has no degradation in latch performance.
BRIEF DESCRIPTION OF THE DRAWINGS
The controller describe herein can be used with different types of circuits to control leakage current within them. It works well with memory systems such as latch, SRAM register file, etc., and as such will be describe in that environment. However, this should not be construed as a limitation on the scope of the invention since it is well within the skills of one skilled in art to make minor changes and adapt the controller for other uses. It is intended that any such modification should be covered by the claims set forth herein.
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Once the CRTL SIG is generated, it is held high until the data line at least changes its state once again during k successive cycles. This is a designated schedule to avoid the power penalty of switching the control signal 114 in the scenario where the data changes too often. For example, we can use a history of 3 cycles; a suitable scheme can be derived based on the function and activity of the data.
In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be appreciated that various modification and changes maybe made thereto without departing from the broader spirit and the scope of the invention set forth in the depending claims. The specification and drawings are accordingly to be regarded in an illustrative rather than being restrictive.
Claims
1. A controller comprising:
- a first circuit arrangement responsive to a control signal to provide a positive rail of a full power supply voltage signal; and
- a second circuit arrangement responsive to said control signal to generate a positive rail of a reduced power supply voltage signal from said full power supply voltage signal.
2. The controller of claim 1 wherein a single device cooperates with the first circuit arrangement and the second circuit arrangement to provide the positive rail of the full power supply voltage and the positive rail of the reduced power supply voltage.
3. The controller of claim 1 further including a third circuit arrangement responsive to said control signal to generate a lower rail of the full power supply voltage signal; and
- a fourth circuit arrangement responsive to said control signal to generate a lower rail of the reduced power supply voltage signal.
4. The controller of claim 3 wherein the lower rail of the full power supply voltage signal includes ground potential and the lower rail of the reduced power supply voltage signal is above said ground potential.
5. The controller of claim 1 wherein the positive rail of the full power supply voltage signal includes 1 volt and the positive rail of the reduced power supply voltage signal includes 0.8 volts.
6. The controller of claim 1 wherein the first circuit arrangement includes:
- a switching gate device for receiving the control signal;
- a first device for providing charging current operatively coupled to said switching gate;
- a first buffer operatively couple to the switching gate; and
- a device for providing the positive rail of the full power supply signal operatively coupled to said buffer.
7. The controller of claim 1 wherein the second circuit arrangement includes:
- a switching gate;
- a first device for supplying charging current operatively coupled to said switching gate;
- a second device operatively coupled to said switching gate;
- a first buffer coupled to the second device; and
- a device for providing the positive rail of the reduced power supply voltage signal operatively coupled to the buffer.
8. The controller of claim 6 further including a second device for providing charging current operatively coupled to the switching gate;
- a second buffer coupled to the second device; and
- a device for providing a ground (Gnd) level potential of the full power supply voltage signal operatively coupled to the second buffer.
9. The controller of claim 7 further including a third device operatively coupled to the switching gate;
- a second buffer coupled to the third device; and
- a device for providing a lower power rail voltage component of said reduced power supply voltage signal operatively coupled to the second buffer.
10. The controller of claim 3 wherein a single device cooperate with the third circuit arrangement and the fourth circuit arrangement to provide the lower rail of the full power supply voltage signal and the lover rail of the reduce voltage signal.
Type: Application
Filed: Jul 19, 2007
Publication Date: Nov 8, 2007
Applicant: International Business Machines Corporation (Armonk, NY)
Inventors: Zhibin Cheng (Cary, NC), Satyajit Dutta (Austin, TX), Peter Klim (Austin, TX)
Application Number: 11/779,991
International Classification: G05F 3/02 (20060101);