Abstract: A photovoltaic device, such as a solar cell, including a copper-containing-grid metallization structure that contains a metal phosphorus layer as a diffusion barrier is provided. The copper-containing-grid metallization structure includes, from bottom to top, an electroplated metal phosphorus layer that does not include copper or a copper alloy located within a grid pattern formed on a front side surface of a semiconductor substrate, and an electroplated copper-containing layer. A method of forming such a structure is also provided.

Abstract: A method for cleaning etch residues that may include treating an etched surface with an aqueous lanthanoid solution, wherein the aqueous lanthanoid solution removes an etch residue that includes a majority of hydrocarbons and at least one element selected from the group consisting of carbon, oxygen, fluorine, nitrogen and silicon. In one example, the aqueous solution may be cerium ammonium nitrate (Ce(NH4)(NO3)),(CAN).

Abstract: A photovoltaic device is provided that includes a semiconductor substrate including a p-n junction with a p-type semiconductor portion and an n-type semiconductor portion one lying on top of the other, wherein an upper exposed surface of the semiconductor substrate represents a front side surface of the semiconductor substrate. A plurality of patterned antireflective coatings is located on the front side surface to provide a grid pattern including a busbar region and finger regions. The busbar region includes at least a real line interposed between at least two dummy lines. A material stack including at least one metal layer located on the semiconductor substrate in the busbar region and the finger regions.

Abstract: Embodiments of the invention include a method of fabrication of a semiconductor structure. The method of fabrication includes: Forming a trench in a first dielectric material down to a first conductive material of a bottom gate. A sidewall of the trench contacts a top surface of the first conductive material. Depositing a second conductive material on the sidewall of the trench, which forms an electrical connection with the first conductive material. Depositing a second dielectric material in the trench, and on the second conductive material. Depositing a gate dielectric material on the second conductive material and the dielectric materials. Forming a channel material on the gate dielectric material. Depositing another conductive material on the channel material and portions of the gate dielectric material to form a source terminal and a drain terminal.

Abstract: A photovoltaic device is provided that includes a semiconductor substrate including a p-n junction with a p-type semiconductor portion and an n-type semiconductor portion one lying on top of the other, wherein an upper exposed surface of the semiconductor substrate represents a front side surface of the semiconductor substrate. A plurality of patterned antireflective coatings is located on the front side surface to provide a grid pattern including a busbar region and finger regions. The busbar region includes at least a real line interposed between at least two dummy lines. A material stack including at least one metal layer located on the semiconductor substrate in the busbar region and the finger regions.

Abstract: A method of forming a photovoltaic device is provided that includes a p-n junction with a p-type semiconductor portion and an n-type semiconductor portion, wherein an upper exposed surface of one of the semiconductor portions represents a front side surface of the semiconductor substrate. Patterned antireflective coating layers are formed on the front side surface of the semiconductor surface to provide a grid pattern including a busbar region and finger region. A mask having a shape that mimics each patterned antireflective coating layer is provided atop each patterned antireflective coating layer. A metal layer is electrodeposited on the busbar region and the finger regions. After removing the mask, an anneal is performed that reacts metal atoms from the metal layer react with semiconductor atoms from the busbar region and the finger regions forming a metal semiconductor alloy.

Abstract: A method for cleaning etch residues that may include treating an etched surface with an aqueous lanthanoid solution, wherein the aqueous lanthanoid solution removes an etch residue that includes a majority of hydrocarbons and at least one element selected from the group consisting of carbon, oxygen, fluorine, nitrogen and silicon. In one example, the aqueous solution may be cerium ammonium nitrate (Ce(NH4)(NO3)),(CAN).

Abstract: A method for cleaning etch residues that may include treating an etched surface with an aqueous lanthanoid solution, wherein the aqueous lanthanoid solution removes an etch residue that includes a majority of hydrocarbons and at least one element selected from the group consisting of carbon, oxygen, fluorine, nitrogen and silicon. In one example, the aqueous solution may be cerium ammonium nitrate (Ce(NH4)(NO3)),(CAN).

Abstract: A photovoltaic device, such as a solar cell, including a copper-containing-grid metallization structure that contains a metal phosphorus layer as a diffusion barrier is provided. The copper-containing-grid metallization structure includes, from bottom to top, an electroplated metal phosphorus layer that does not include copper or a copper alloy located within a grid pattern formed on a front side surface of a semiconductor substrate, and an electroplated copper-containing layer. A method of forming such a structure is also provided.

Abstract: Embodiments of the invention include a method of fabrication of a semiconductor structure. The method of fabrication includes: Forming a trench in a first dielectric material down to a first conductive material of a bottom gate. A sidewall of the trench contacts a top surface of the first conductive material. Depositing a second conductive material on the sidewall of the trench, which forms an electrical connection with the first conductive material. Depositing a second dielectric material a in the trench, and on the second conductive material. Depositing a gate dielectric material on the second conductive material and the dielectric materials. Forming a channel material on the gate dielectric material. Depositing another conductive material on the channel material and portions of the gate dielectric material to form a source terminal and a drain terminal.

Abstract: A photovoltaic device, such as a solar cell, including a copper-containing-grid metallization structure that contains a metal phosphorus layer as a diffusion barrier is provided. The copper-containing-grid metallization structure includes, from bottom to top, an electroplated metal phosphorus layer that does not include copper or a copper alloy located within a grid pattern formed on a front side surface of a semiconductor substrate, and an electroplated copper-containing layer. A method of forming such a structure is also provided.

Abstract: A photovoltaic device is provided that includes a semiconductor substrate including a p-n junction with a p-type semiconductor portion and an n-type semiconductor portion one on top of the other. A plurality of patterned antireflective coating layers is located on a p-type semiconductor surface of the semiconductor substrate, wherein at least one portion of the p-type semiconductor surface of the semiconductor substrate is exposed. Aluminum is located directly on the at least one portion of the p-type semiconductor surface of the semiconductor substrate that is exposed.

Abstract: Embodiments of the invention include a method of fabrication and a semiconductor structure. The method of fabrication includes depositing a first dielectric material on a substrate, and forming a bottom gate including filling a first opening in the first dielectric layer with a first conductive material. Next, depositing a second dielectric material, and forming a trench in the second dielectric material down to the first conductive material. Next, depositing a second conductive material on the sidewall of the trench forming an electrical connection between the first conductive material and the second conductive material, depositing a third dielectric material in the trench, and removing excess material not in the trench. Next, depositing a gate dielectric layer, and forming a channel layer of carbon nanotubes on the gate dielectric layer. Lastly, depositing a third conductive material on the channel layer forming source and drain terminals.

Abstract: An anti-retraction capping material is formed on a surface of a nanowire that is located upon a dielectric membrane. A gap is then formed into the anti-retraction capping material and nanowire forming first and second capped nanowire structures of a nanodevice. The nanodevice can be used for recognition tunneling measurements including, for example DNA sequencing. The anti-retraction capping material serves as a mobility barrier to pin, i.e., confine, a nanowire portion of each of the first and second capped nanowire structures in place, allowing long-term structural stability. In some embodiments, interelectrode leakage through solution during recognition tunneling measurements can be minimized.

Abstract: A technique is provided for manufacturing a nanogap in a nanodevice. An oxide is disposed on a wafer. A nanowire is disposed on the oxide. A helium ion beam is applied to cut the nanowire into a first nanowire part and a second nanowire part which forms the nanogap in the nanodevice. Applying the helium ion beam to cut the nanogap forms a signature of nanowire material in proximity to at least one opening of the nanogap.

Abstract: A technique is provided for manufacturing a nanogap in a nanodevice. An oxide is disposed on a wafer. A nanowire is disposed on the oxide. A helium ion beam is applied to cut the nanowire into a first nanowire part and a second nanowire part which forms the nanogap in the nanodevice. Applying the helium ion beam to cut the nanogap forms a signature of nanowire material in proximity to at least one opening of the nanogap.

Abstract: An anti-retraction capping material is formed on a surface of a nanowire that is located upon a dielectric membrane. A gap is then formed into the anti-retraction capping material and nanowire forming first and second capped nanowire structures of a nanodevice. The nanodevice can be used for recognition tunneling measurements including, for example DNA sequencing. The anti-retraction capping material serves as a mobility barrier to pin, i.e., confine, a nanowire portion of each of the first and second capped nanowire structures in place, allowing long-term structural stability. In some embodiments, interelectrode leakage through solution during recognition tunneling measurements can be minimized.

Abstract: Embodiments of the invention include a method of fabrication and a semiconductor structure. The method of fabrication includes depositing a first dielectric material on a substrate, and forming a bottom gate comprising filling a first opening in the first dielectric layer with a first conductive material. Next, depositing a second dielectric material, and forming a trench in the second dielectric material down to the first conductive material. Next, depositing a second conductive material on the sidewall of the trench forming an electrical connection between the first conductive material and the second conductive material, depositing a third dielectric material in the trench, and removing excess material not in the trench. Next, depositing a gate dielectric layer, and forming a channel layer of carbon nanotubes on the gate dielectric layer. Lastly, depositing a third conductive material on the channel layer forming source and drain terminals.

Abstract: A technique is provided for manufacturing a nanogap in a nanodevice. An oxide is disposed on a wafer. A nanowire is disposed on the oxide. A helium ion beam is applied to cut the nanowire into a first nanowire part and a second nanowire part which forms the nanogap in the nanodevice. Applying the helium ion beam to cut the nanogap forms a signature of nanowire material in proximity to at least one opening of the nano gap.

Abstract: A technique is provided for manufacturing a nanogap in a nanodevice. An oxide is disposed on a wafer. A nanowire is disposed on the oxide. A helium ion beam is applied to cut the nanowire into a first nanowire part and a second nanowire part which forms the nanogap in the nanodevice. Applying the helium ion beam to cut the nanogap forms a signature of nanowire material in proximity to at least one opening of the nano gap.