Patents by Inventor Scott Barnett Swaney
Scott Barnett Swaney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8135960Abstract: A multiprocessor electronic circuit and an electronic data processing system comprising such circuit are disclosed for reducing the power consumption and the chip area consumption of a multiprocessor system having cryptographic functionality. In one embodiment, the multiprocessor electronic circuit comprises a plurality of processors, a single cryptographic processing unit that comprises a plurality of input/output buffer pairs and two cryptographic engines, a cipher engine and a hash engine, and associated control logic.Type: GrantFiled: October 9, 2008Date of Patent: March 13, 2012Assignee: International Business Machines CorporationInventors: Thomas Koehler, Thomas Fuchs, Ulrich Mayer, Chung-Lung Kevin Shum, Scott Barnett Swaney
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Patent number: 8122297Abstract: A method and apparatus are disclosed for performing maintenance operations in a system using address, data, and controls which are transported through the system, allowing for parallel and serial operations to co-exist without the parallel operations being slowed down by the serial ones. It also provides for use of common shifters, engines, and protocols as well as efficient conversion of ECC to parity and parity to ECC as needed in the system. The invention also provides for error detection and isolation, both locally and in the reported status. The invention provides for large maintenance address and data spaces (typically 64 bits address and 64 bits data per address supported).Type: GrantFiled: October 18, 2007Date of Patent: February 21, 2012Assignee: International Business Machines CorporationInventors: Patrick J. Meaney, Ra'ed Mohammad Al-Omari, Michael Francis Fee, Pak-kin Mak, Scott Barnett Swaney
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Patent number: 8090929Abstract: A digital system and method of operating the same. The system comprises a processor chip including a first elastic interface domain, wherein the first elastic interface domain comprises a first processor X logic and a first processor Y logic, wherein the first processor X and Y logic comprise first X and Y latches, respectively; and a first ASIC chip electrically coupled to the processor chip, wherein the first processor X and Y logics are configured to be simultaneously in a functional mode, wherein the first processor X logic is configured to switch from the functional mode to a scanning mode while the first processor Y logic remains in the functional mode, and wherein in response to the first processor Y logic being in the functional mode, the first processor Y logic is configured to generate a first reference ASIC clock signal to the first ASIC chip.Type: GrantFiled: September 24, 2008Date of Patent: January 3, 2012Assignee: International Business Machines CorporationInventors: Jeffrey A. Magee, Timothy Gerard McNamara, Walter Niklaus, Scott Barnett Swaney, Tobias Webel
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Patent number: 8090823Abstract: Illustrative embodiments disclose a data processing system providing low-level hardware access to in-band and out-of-band firmware. The data processing system includes a plurality of chips that includes at least one processor chip and a plurality of support chips. At least one processor chip includes a field replaceable unit support interface master that uses a field replaceable unit support interface serial transmission protocol to communicate with the plurality of support chips. Each one of the plurality of support chips includes a field replaceable unit support interface slave in, with ones of the plurality of chips that include a processor also include the field replaceable unit support interface master, and ones of the plurality of chips that do not include the processor include only the field replaceable unit support interface slave. Only the field replaceable unit support interface master possesses conversion logic.Type: GrantFiled: October 28, 2008Date of Patent: January 3, 2012Assignee: International Business Machines CorporationInventors: James Stephen Fields, Jr., Paul Frank Lecocq, Brian Chan Monwai, Thomas Pflueger, Kevin Franklin Reick, Timothy M. Skergan, Scott Barnett Swaney
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Patent number: 7966536Abstract: A method for automatic scan completion in the event of a system checkstop in a processor. The processor includes: a processor register; a millicode interface connected between the processor register and a checkstop scan controller; a checkstop logic circuit connected between the checkstop scan controller and a checkstop scan engine; and a scan chain engine and a scan chain connected to the checkstop scan engine. The method includes (a) upon occurrence of a checkstop serially reading data from a processor register and serially writing the data to latches of a scan chain register; and (b) upon occurrence of a system checkstop during (a), stopping the reading and writing and moving data sent before the system checkstop from latches of the scan chain where the data was stored when the system checkstop occurred to latches where the data would have been stored if the system checkstop had not occurred.Type: GrantFiled: April 11, 2008Date of Patent: June 21, 2011Assignee: International Business Machines CorporationInventors: Ralf Ludewig, Walter Niklaus, Dietmar Schmunkamp, Scott Barnett Swaney, Tobias Webel
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Patent number: 7916722Abstract: A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface on a processor chip. The memory-mapped support interface updates memory, memory-mapped registers or memory-mapped resources. The interface uses fabric packet generation logic to generate a single command packet in a protocol for the coherency fabric which consists of an address, command and/or data. Fabric commands are converted to FSI protocol and forwarded to attached support chips to access the memory-mapped resource, and responses from the support chips are converted back to fabric response packets. Fabric snoop logic monitors the coherency fabric and decodes responses for packets previously sent by fabric packet generation logic. The fabric snoop logic updates status register and/or writes response data to a read data register. The system also reports any errors that are encountered.Type: GrantFiled: June 16, 2008Date of Patent: March 29, 2011Assignee: International Business Machines CorporationInventors: James Stephen Fields, Jr., Paul Frank Lecocq, Brian Chan Monwai, Thomas Pflueger, Kevin Franklin Reick, Timothy M. Skergan, Scott Barnett Swaney
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Patent number: 7870406Abstract: Mechanism for accurately measuring useful capacity of a processor allocated to each thread in a simultaneously multi-threading data processing system. Instructions dispatched from multiple threads are executed by the processor on a same clock cycle. A determination is made whether Time Base (TB) register bit (60) is changing. A dispatch charge value is determined for each thread, and added to the Processor Utilization Resource Register for each thread when TB bit (60) changes.Type: GrantFiled: February 3, 2005Date of Patent: January 11, 2011Assignee: International Business Machines CorporationInventors: Richard Louis Arndt, Balaram Sinharoy, Scott Barnett Swaney, Kenneth Lundy Ward
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Patent number: 7865758Abstract: Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set.Type: GrantFiled: June 16, 2008Date of Patent: January 4, 2011Assignee: International Business Machines CorporationInventors: Scott Barnett Swaney, Kenneth Lundy Ward, Tobias Webel, Ulrich Weiss, Matthias Woehrle
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Patent number: 7840860Abstract: A method and system is presented for correcting a data error in a primary Dynamic Random Access Memory (DRAM) in a Dual In-line Memory Module (DIMM). Each DRAM has a left half (for storing bits 0:3) and a right half (for storing bits 4:7). A determination is made as to whether the data error was in the left or right half of the primary DRAM. The half of the primary DRAM in which the error occurred is removed from service. All subsequent reads and writes for data originally stored in the primary DRAM's defective half are made to a half of a spare DRAM in the DIMM, while the DRAM's non-defective half continues to be used for subsequently storing data.Type: GrantFiled: August 7, 2008Date of Patent: November 23, 2010Assignee: International Business Machines CorporationInventors: Luiz Carlos Alves, Mark Andrew Brittain, Timothy Jay Dell, Sanjeev Ghai, Warren Edward Maule, Scott Barnett Swaney
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Patent number: 7827443Abstract: Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.Type: GrantFiled: November 13, 2008Date of Patent: November 2, 2010Assignee: International Business Machines CorporationInventors: Susan Elizabeth Eisen, Hung Qui Le, Michael James Mack, Dung Quoc Nguyen, Jose Angel Paredes, Scott Barnett Swaney
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Patent number: 7761726Abstract: Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set.Type: GrantFiled: May 7, 2008Date of Patent: July 20, 2010Assignee: International Business Machines CorporationInventors: Scott Barnett Swaney, Kenneth Lundy Ward, Tobias Webel, Ulrich Weiss, Matthias Woehrle
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Patent number: 7707452Abstract: A system and method of recovering from errors in a data processing system. The data processing system includes one or more processor cores coupled to one or more memory controllers. The one or more memory controllers include at least a first memory interface coupled to a first memory and at least a second memory interface coupled to a second memory. In response to determining an error has been detected in the first memory, access to the first memory via the first memory interface is inhibited. Also, the first memory interface is locally restarted without restarting the second memory interface.Type: GrantFiled: June 9, 2008Date of Patent: April 27, 2010Assignee: International Business Machines CorporationInventors: Edgar Rolando Cordero, James Stephen Fields, Jr., Kevin Charles Gower, Eric Eugene Retter, Scott Barnett Swaney
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Patent number: 7624318Abstract: A computer implemented method, a data processing system, and a computer usable program code for automatically identifying multiple combinations of operational and non-operational components with a single part number. A non-volatile storage is provided on a part, wherein the part includes a plurality of sub-components. Unavailable sub-components in the plurality of sub-components are identified based on a series of testing to form identified unavailable sub-components. Information of the identified unavailable sub-components is stored into the non-volatile storage.Type: GrantFiled: September 27, 2005Date of Patent: November 24, 2009Assignee: International Business Machines CorporationInventors: Andreas Bieswanger, Herwig Elfering, James Stephen Fields, Jr., Andrew J. Geissler, Alan Hlava, Scott Barnett Swaney
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Publication number: 20090259899Abstract: A method for automatic scan completion in the event of a system checkstop in a processor. The processor includes: a processor register; a millicode interface connected between the processor register and a checkstop scan controller; a checkstop logic circuit connected between the checkstop scan controller and a checkstop scan engine; and a scan chain engine and a scan chain connected to the checkstop scan engine. The method includes (a) upon occurrence of a checkstop serially reading data from a processor register and serially writing the data to latches of a scan chain register; and (b) upon occurrence of a system checkstop during (a), stopping the reading and writing and moving data sent before the system checkstop from latches of the scan chain where the data was stored when the system checkstop occurred to latches where the data would have been stored if the system checkstop had not occurred.Type: ApplicationFiled: April 11, 2008Publication date: October 15, 2009Inventors: Ralf Ludewig, Walter Niklaus, Dietmar Schmunkamp, Scott Barnett Swaney, Tobias Webel
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Publication number: 20090217000Abstract: A digital system and method of operating the same. The system comprises a processor chip including a first elastic interface domain, wherein the first elastic interface domain comprises a first processor X logic and a first processor Y logic, wherein the first processor X and Y logic comprise first X and Y latches, respectively; and a first ASIC chip electrically coupled to the processor chip, wherein the first processor X and Y logics are configured to be simultaneously in a functional mode, wherein the first processor X logic is configured to switch from the functional mode to a scanning mode while the first processor Y logic remains in the functional mode, and wherein in response to the first processor Y logic being in the functional mode, the first processor Y logic is configured to generate a first reference ASIC clock signal to the first ASIC chip.Type: ApplicationFiled: September 24, 2008Publication date: August 27, 2009Inventors: Jeffrey A. Magee, Timothy Gerard McNamara, Walter Niklaus, Scott Barnett Swaney, Tobias Webel
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Patent number: 7568138Abstract: A computer implemented method and data processing system are provided for preventing firmware defects from disrupting logic clocks. In response to a firmware interface requesting a scan operation for a functional unit, protection logic allows a scan enable to activate to the functional unit only if the logic clocks are stopped to that functional unit, otherwise the scan enable is not activated, an error is indicated, and an interrupt is presented to firmware. Also, in response to a command from a firmware interface to stop the logic clocks to a functional unit, protection logic allows the clocks to be stopped to the functional unit only if the functional unit is already indicating a catastrophic error, otherwise the clocks are not stopped, an error is indicated, and an interrupt is presented to firmware.Type: GrantFiled: July 26, 2006Date of Patent: July 28, 2009Assignee: International Business Machines CorporationInventors: Adolf Martens, Walter Niklaus, Dietmar Schmunkamp, Scott Barnett Swaney, Ching-Lung L. Tong, Tobias Webel
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Publication number: 20090113212Abstract: A multiprocessor electronic circuit and an electronic data processing system comprising such circuit are disclosed for reducing the power consumption and the chip area consumption of a multiprocessor system having cryptographic functionality. In one embodiment, the multiprocessor electronic circuit comprises a plurality of processors, a single cryptographic processing unit that comprises a plurality of input/output buffer pairs and two cryptographic engines, a cipher engine and a hash engine, and associated control logic.Type: ApplicationFiled: October 9, 2008Publication date: April 30, 2009Applicant: International Business Machines CorporationInventors: Thomas Koehler, Thomas Fuchs, Ulrich Mayer, Chung-Lung Kevin Shum, Scott Barnett Swaney
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Publication number: 20090106588Abstract: A method and apparatus are disclosed for performing maintenance operations in a system using address, data, and controls which are transported through the system, allowing for parallel and serial operations to co-exist without the parallel operations being slowed down by the serial ones. It also provides for use of common shifters, engines, and protocols as well as efficient conversion of ECC to parity and parity to ECC as needed in the system. The invention also provides for error detection and isolation, both locally and in the reported status. The invention provides for large maintenance address and data spaces (typically 64 bits address and 64 bits data per address supported).Type: ApplicationFiled: October 18, 2007Publication date: April 23, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Patrick J. Meaney, Ra'ed Mohammad Al-Omari, Michael Francis Fee, Pak-kin Mak, Scott Barnett Swaney
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Patent number: 7523364Abstract: A method and system is presented for correcting a data error in a primary Dynamic Random Access Memory (DRAM) in a Dual In-line Memory Module (DIMM). Each DRAM has a left half (for storing bits 0:3) and a right half (for storing bits 4:7). A determination is made as to whether the data error was in the left or right half of the primary DRAM. The half of the primary DRAM in which the error occurred is removed from service. All subsequent reads and writes for data originally stored in the primary DRAM's defective half are made to a half of a spare DRAM in the DIMM, while the DRAM's non-defective half continues to be used for subsequently storing data.Type: GrantFiled: February 9, 2005Date of Patent: April 21, 2009Assignee: International Business Machines CorporationInventors: Luiz Carlos Alves, Mark Andrew Brittain, Timothy Jay Dell, Sanjeev Ghai, Warren Edward Maule, Scott Barnett Swaney
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Patent number: 7512826Abstract: A method, apparatus, and computer program product are disclosed in a data processing system for providing a virtualized time base in a logically partitioned data processing system. A time base is determined for each one of multiple processor cores. The time base is used to indicate a current time to one of the processor cores for which the time base is determined. The time bases are synchronized together for the processor cores such that each one of the processor cores includes its own copy of a synchronized time base. For one of the processor cores, a virtualized time base is generated that is different from the synchronized time base but that remains synchronized with at least a portion of the synchronized time base. The processor core utilizes the virtualized time base instead of the synchronized time base for indicating the current time to the processor core. The synchronized time bases and the portion of the virtualized time base remaining in synchronization together.Type: GrantFiled: April 20, 2005Date of Patent: March 31, 2009Assignee: International Business Machines CorporationInventors: William Joseph Armstrong, Michael J. Corrigan, Naresh Nayar, Scott Barnett Swaney