Patents by Inventor Scott Barnett Swaney
Scott Barnett Swaney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20090063898Abstract: Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.Type: ApplicationFiled: November 13, 2008Publication date: March 5, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Susan Elizabeth Eisen, Hung Qui Le, Michael James Mack, Dung Quoc Nguyen, Jose Angel Paredes, Scott Barnett Swaney
-
Publication number: 20090055563Abstract: In-band firmware executes instructions which cause commands to be sent on a coherency fabric. Fabric snoop logic monitors the coherency fabric for command packets that target a resource in one of the support chips attached via an FSI link. Conversion logic converts the information from the fabric packet into an FSI protocol. An FSI command is transmitted via the FSI transmit link to an FSI slave of the intended support chip. An FSI receive link receives response data from the FSI slave of the intended support chip. Conversion logic converts the information from the support chip received via the FSI receive link into the fabric protocol. Response packet generation logic generates the fabric response packet and returns it on the coherency fabric. An identical FSI link between a support processor and support chips allows direct access to the same resources on the support chips by out-of-band firmware.Type: ApplicationFiled: October 28, 2008Publication date: February 26, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James Stephen Fields, JR., Paul Frank Lecocq, Brian Chan Monwai, Thomas Pflueger, Kevin Franklin Reick, Timothy M. Skergan, Scott Barnett Swaney
-
Patent number: 7487377Abstract: Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set.Type: GrantFiled: February 9, 2005Date of Patent: February 3, 2009Assignee: International Business Machines CorporationInventors: Scott Barnett Swaney, Kenneth Lundy Ward, Tobias Webel, Ulrich Weiss, Matthias Woehrle
-
Patent number: 7478276Abstract: A method and apparatus are provided for dispatch group checkpointing in a microprocessor, including provisions for handling partially completed dispatch groups and instructions which modify system coherent state prior to completion. An instruction checkpoint retry mechanism is implemented to recover from soft errors in logic. The processor is able to dispatch fixed point unit (FXU), load/store unit (LSU), and floating point unit (FPU) or vector multimedia extension (VMX) instructions on the same cycle. Store data is written to a store queue when a store instruction finishes executing. The data is held in the store queue until the store instruction is checkpointed, at which point it can be released to the coherently shared level 2 (L2) cache.Type: GrantFiled: February 10, 2005Date of Patent: January 13, 2009Assignee: International Business Machines CorporationInventors: James Wilson Bishop, Hung Qui Le, Michael James Mack, Jafar Nahidi, Dung Quoc Nguyen, Jose Angel Paredes, Scott Barnett Swaney, Brian William Thompto
-
Patent number: 7467325Abstract: Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.Type: GrantFiled: February 10, 2005Date of Patent: December 16, 2008Assignee: International Business Machines CorporationInventors: Susan Elizabeth Eisen, Hung Qui Le, Michael James Mack, Dung Quoc Nguyen, Jose Angel Paredes, Scott Barnett Swaney
-
Patent number: 7467204Abstract: In-band firmware executes instructions which cause commands to be sent on a coherency fabric. Fabric snoop logic monitors the coherency fabric for command packets that target a resource in one of the support chips attached via an FSI link. Conversion logic converts the information from the fabric packet into an FSI protocol. An FSI command is transmitted via the FSI transmit link to an FSI slave of the intended support chip. An FSI receive link receives response data from the FSI slave of the intended support chip. Conversion logic converts the information from the support chip received via the FSI receive link into the fabric protocol. Response packet generation logic generates the fabric response packet and returns it on the coherency fabric. An identical FSI link between a support processor and support chips allows direct access to the same resources on the support chips by out-of-band firmware.Type: GrantFiled: February 10, 2005Date of Patent: December 16, 2008Assignee: International Business Machines CorporationInventors: James Stephen Fields, Jr., Paul Frank Lecocq, Brian Chan Monwai, Thomas Pflueger, Kevin Franklin Reick, Timothy M. Skergan, Scott Barnett Swaney
-
Publication number: 20080294950Abstract: A method and system is presented for correcting a data error in a primary Dynamic Random Access Memory (DRAM) in a Dual In-line Memory Module (DIMM). Each DRAM has a left half (for storing bits 0:3) and a right half (for storing bits 4:7). A determination is made as to whether the data error was in the left or right half of the primary DRAM. The half of the primary DRAM in which the error occurred is removed from service. All subsequent reads and writes for data originally stored in the primary DRAM's defective half are made to a half of a spare DRAM in the DIMM, while the DRAM's non-defective half continues to be used for subsequently storing data.Type: ApplicationFiled: August 7, 2008Publication date: November 27, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Luiz Carlos Alves, Mark Andrew Brittain, Timothy Jay Dell, Sanjeev Ghai, Warren Edward Maule, Scott Barnett Swaney
-
Publication number: 20080270821Abstract: A system and method of recovering from errors in a data processing system. The data processing system includes one or more processor cores coupled to one or more memory controllers. The one or more memory controllers include at least a first memory interface coupled to a first memory and at least a second memory interface coupled to a second memory. In response to determining an error has been detected in the first memory, access to the first memory via the first memory interface is inhibited. Also, the first memory interface is locally restarted without restarting the second memory interface.Type: ApplicationFiled: June 9, 2008Publication date: October 30, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORP.Inventors: Edgar Rolando Cordero, James Stephen Fields, Kevin Charles Gower, Eric Eugene Retter, Scott Barnett Swaney
-
Publication number: 20080247415Abstract: A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface on a processor chip. The memory-mapped support interface updates memory, memory-mapped registers or memory-mapped resources. The interface uses fabric packet generation logic to generate a single command packet in a protocol for the coherency fabric which consists of an address, command and/or data. Fabric commands are converted to FSI protocol and forwarded to attached support chips to access the memory-mapped resource, and responses from the support chips are converted back to fabric response packets. Fabric snoop logic monitors the coherency fabric and decodes responses for packets previously sent by fabric packet generation logic. The fabric snoop logic updates status register and/or writes response data to a read data register. The system also reports any errors that are encountered.Type: ApplicationFiled: June 16, 2008Publication date: October 9, 2008Applicant: INTERNATIONAL BUSINESS MACHINE CORPORATIONInventors: James Stephen Fields, Paul Frank Lecocq, Brian Chan Monwai, Thomas Pflueger, Kevin Franklin Reick, Timothy M. Skergan, Scott Barnett Swaney
-
Publication number: 20080244300Abstract: Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set.Type: ApplicationFiled: June 16, 2008Publication date: October 2, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Scott Barnett Swaney, Kenneth Lundy Ward, Tobias Webel, Ulrich Weiss, Matthias Woehrle
-
Publication number: 20080215906Abstract: Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set.Type: ApplicationFiled: May 7, 2008Publication date: September 4, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Scott Barnett Swaney, Kenneth Lundy Ward, Tobias Webel, Ulrich Weiss, Matthias Woehrle
-
Patent number: 7418541Abstract: A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface on a processor chip. The memory-mapped support interface updates memory, memory-mapped registers or memory-mapped resources. The interface uses fabric packet generation logic to generate a single command packet in a protocol for the coherency fabric which consists of an address, command and/or data. Fabric commands are converted to FSI protocol and forwarded to attached support chips to access the memory-mapped resource, and responses from the support chips are converted back to fabric response packets. Fabric snoop logic monitors the coherency fabric and decodes responses for packets previously sent by fabric packet generation logic. The fabric snoop logic updates status register and/or writes response data to a read data register. The system also reports any errors that are encountered.Type: GrantFiled: February 10, 2005Date of Patent: August 26, 2008Assignee: International Business Machines CorporationInventors: James Stephen Fields, Jr., Paul Frank Lecocq, Brian Chan Monwai, Thomas Pflueger, Kevin Franklin Reick, Timothy M. Skergan, Scott Barnett Swaney
-
Patent number: 7409580Abstract: A system and method of recovering from errors in a data processing system. The data processing system includes one or more processor cores coupled to one or more memory controllers. The one or more memory controllers include at least a first memory interface coupled to a first memory and at least a second memory interface coupled to a second memory. In response to determining an error has been detected in the first memory, access to the first memory via the first memory interface is inhibited. Also, the first memory interface is locally restarted without restarting the second memory interface.Type: GrantFiled: February 9, 2005Date of Patent: August 5, 2008Assignee: International Business Machines CorporationInventors: Edgar Rolando Cordero, James Stephen Fields, Jr., Kevin Charles Gower, Eric Eugene Retter, Scott Barnett Swaney
-
Publication number: 20080028266Abstract: A computer implemented method and data processing system are provided for preventing firmware defects from disrupting logic clocks. In response to a firmware interface requesting a scan operation for a functional unit, protection logic allows a scan enable to activate to the functional unit only if the logic clocks are stopped to that functional unit, otherwise the scan enable is not activated, an error is indicated, and an interrupt is presented to firmware. Also, in response to a command from a firmware interface to stop the logic clocks to a functional unit, protection logic allows the clocks to be stopped to the functional unit only if the functional unit is already indicating a catastrophic error, otherwise the clocks are not stopped, an error is indicated, and an interrupt is presented to firmware.Type: ApplicationFiled: July 26, 2006Publication date: January 31, 2008Inventors: Adolf Martens, Walter Niklaus, Dietmar Schmunkamp, Scott Barnett Swaney, Ching-Lung L. Tong, Tobias Webel
-
Patent number: 5692121Abstract: A method for making a processor system immune to circuit failure caused by external noise using mirrored processors, and a recovery unit integral with the method, are disclosed. Identical addresses and data information is generated in each of two processors. The data is then partitioned into registers and Error Correction Codes (ECC's) are generated for the data. The address, data, and ECC information for each processor is then interlaced in a data structure. The interlaced structures of each processor are then compared. If the comparison yields no errors, the data is checkpointed in the recovery unit; if an error is detected, a recovery sequence can be initiated after the check-stop operation, whereby the system is restored to the last error-free checkpointing operation.Type: GrantFiled: April 30, 1996Date of Patent: November 25, 1997Assignee: International Business Machines CorporationInventors: Ferenc Miklos Bozso, Yiu-Hing Chan, Philip George Emma, Algirdas Joseph Gruodis, David Patrick Hillerud, Scott Barnett Swaney
-
Patent number: 5673391Abstract: Retry trap in the processor system detects the occurrence of a hardware retry during a millicode routine. In operation, millicode resets the retry trap to "O" at the start of a millicode sequence that is sensitive to a retry operation being at some stage of the millicode sequence. The millicode routine tests the retry latch state at one or more points in the sequence to determine if a retry has occurred since the start of the sequence, which is sensitive to a retry operation. The action taken in response to a determination that a retry operation has occurred depends upon the type of potential damage to the system state as a result of the occurrence of the retry operation during the millicode sequence.Type: GrantFiled: March 31, 1995Date of Patent: September 30, 1997Assignee: International Business Machines CorporationInventors: Charles Franklin Webb, Mark Steven Farrell, Scott Barnett Swaney