Patents by Inventor Scott D. Luning
Scott D. Luning has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6127222Abstract: A system and method for providing a flash memory cell on a semiconductor substrate are disclosed. The system and method include providing a side implant and providing an implant in at least one of a drain or a source of the flash memory cell.Type: GrantFiled: December 16, 1997Date of Patent: October 3, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Scott D. Luning, Mark Randolph
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Patent number: 6051882Abstract: A method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a reverse damascene in the formation of the conductive lines and vias. A conductive line pattern is first used to etch completely through the layer to form conductive line openings. The openings are completely filled with a conductive material and planarized so that the surfaces of the conductive material and the insulating layer are coplanar. A via pattern is aligned perpendicular to the conductive lines and the conductive material is etched half way through the conductive lines in other than the areas covered by the via pattern. The openings thus created in the upper portion of the conductive lines are filled with insulating material to complete the dual damascene interconnection level with the conductive lines in the lower portion of the insulating layer and upwardly projecting vias in the upper portion of the layer.Type: GrantFiled: August 5, 1997Date of Patent: April 18, 2000Assignee: Advanced Micro DevicesInventors: Steven Avanzino, Subhash Gupta, Rich Klein, Scott D. Luning, Ming-Rin Lin
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Patent number: 6025240Abstract: A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at least one gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system include providing at least one gate stack on the semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The at least one gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack.Type: GrantFiled: December 18, 1997Date of Patent: February 15, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Vei-Han Chan, Scott D. Luning, Mark Randolph, Nicholas H. Tripsas, Daniel Sobek, Janet Wang, Timothy J. Thurgate, Sameer Haddad
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Patent number: 6015736Abstract: A system and method for providing at least one memory cell on a semiconductor is disclosed. The method and system include providing a tunneling barrier on the semiconductor, providing at least one floating gate having a corner, and oxidizing the tunneling barrier, a portion of the semiconductor, and the at least one floating gate. A portion of the at least one floating gate including the corner is disposed above the tunneling barrier. The portion of the semiconductor oxidizes at a first rate and at least the corner of the at least one floating gate oxidizes at a second rate. The second rate is sufficiently higher than the first rate to provide a desired thickness of the tunneling barrier a distance from the corner of the at least one floating gate for a particular rounding of the corner of the at least one floating gate.Type: GrantFiled: December 19, 1997Date of Patent: January 18, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Scott D. Luning, Mark Randolph
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Patent number: 6005279Abstract: An insulating trench isolation structure is formed in a semiconductor substrate with a spacer overlying the trench edge to prevent oxide loss during subsequent etching, thereby preventing junction leakage, particulary upon silicidation. Embodiments include providing a step in the trench fill and forming the nitride spacer during gate electrode sidewall spacer formation. The protective nitride spacer etches more slowly than oxide and, hence, remains after subsequent oxide etching and cleaning.Type: GrantFiled: December 18, 1997Date of Patent: December 21, 1999Assignee: Advanced Micro Devices, Inc.Inventor: Scott D. Luning
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Patent number: 6005808Abstract: A method and apparatus for reducing band-to-band currents during the erasure of a flash EEPROM memory cell is provided. The apparatus has a back biasing connection on the substrate at which a biasing voltage is applied during erasure of the flash EEPROM memory cell. The method of applying the biasing voltage to the back biasing connection during erasure of the flash EEPROM memory cell reduces band-to-band current between the source region and the substrate during erasure of the flash memory cell. This reduction provides for gate size reduction in flash memory cells without inducing detrimental short channel effects.Type: GrantFiled: December 18, 1997Date of Patent: December 21, 1999Assignee: Advanced Micro Devices, Inc.Inventors: Daniel Sobek, Timothy James Thurgate, Scott D. Luning, Vei-Han Chan, Sameer S. Haddad
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Patent number: 5989963Abstract: A method of manufacturing a semiconductor device with a steep retrograde profile. The threshold voltage adjust dopant layer and the punchthrough prevent dopant layer are formed in the substrate. All surface capping layers are removed from the active device regions and, the semiconductor device is placed in a chamber and a high vacuum is established after which an inert atmosphere is introduced into the chamber. The anneal to repair the damage to the lattice and to activate the dopant ions in the dopant layers is done in the inert atmosphere with the surface of the substrate maintained clean, that is, free from a capping oxide or other layer formed on the surface of the substrate.Type: GrantFiled: July 21, 1997Date of Patent: November 23, 1999Assignee: Advanced Micro Devices, Inc.Inventors: Scott D. Luning, David C. Greenlaw, Jonathan Fewkes
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Patent number: 5888867Abstract: Aspects for forming a Flash EPROM cell with an adjustable threshold voltage are described. In a method aspect, the method includes forming a substrate structure to establish a foundation for cell formation, and forming a gate structure with a floating gate layer comprising polysilicon-germanium (poly-SiGe) of a non-uniform Ge concentration on the substrate structure. The method further includes forming source and drain regions within the substrate structure, the drain region having a different threshold voltage than the source region. In a further aspect, a Flash EPROM cell with an adjustable threshold voltage includes a substrate structure as a foundation for the cell. The cell further includes a gate structure on the substrate structure, the gate structure comprising a floating gate layer of polysilicon-germanium (poly-SiGe) of non-uniform Ge concentration.Type: GrantFiled: February 13, 1998Date of Patent: March 30, 1999Assignee: Advanced Micro Devices, Inc.Inventors: Janet Wang, Scott D. Luning, Vei-Han Chan, Nicholas H. Tripsas
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Patent number: 5795823Abstract: A method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using dual damascene with only one mask pattern for the formation of both the conductive lines and vias. The mask pattern of conductive lines contains laterally enlarged areas where the via openings are to formed in the insulating material. After the conductive line openings with laterally enlarged areas are created, the openings are filled with a conformal material whose etch selectivity is substantially less than the etch selectivity of the insulating material to the enchant for etching the insulating material and whose etch selectivity is substantially greater than the insulating material to its enchant. The conformal material is anisotropically etched to form sidewalls in the enlarged area and remove the material between the sidewalls but leave material remaining in the parts of the conductive lines openings.Type: GrantFiled: November 20, 1996Date of Patent: August 18, 1998Assignee: Advanced Micro Devices, Inc.Inventors: Steven Avanzino, Subhash Gupta, Rich Klein, Scott D. Luning, Ming-Ren Lin
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Patent number: 5705430Abstract: A dual damascene method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a sacrificial via fill. A first layer of insulating material is formed with via openings. The openings are filled with a sacrificial removable material. A second layer of insulating material is deposed on the first layer. In one embodiment, the etch selectivity to the etchant of the second layer is essentially the same as the sacrificial via fill and, preferably, is substantially higher than second layer. Using a conductive line pattern aligned with the via openings, conductive line openings are etched in the second insulating layer and, during etching, the sacrificial fill is removed from the via openings.Type: GrantFiled: June 7, 1995Date of Patent: January 6, 1998Assignee: Advanced Micro Devices, Inc.Inventors: Steven Avanzino, Subhash Gupta, Rich Klein, Scott D. Luning, Ming-Ren Lin
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Patent number: 5691238Abstract: A method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a reverse damascene in the formation of the conductive lines and vias. A conductive line pattern is first used to etch completely through the layer to form conductive line openings. The openings are completely filled with a conductive material and planarized so that the surfaces of the conductive material and the insulating layer are coplanar. A via pattern is aligned perpendicular to the conductive lines and the conductive material is etched half way through the conductive lines in other than the areas covered by the via pattern. The openings thus created in the upper portion of the conductive lines are filled with insulating material to complete the dual damascene interconnection level with the conductive lines in the lower portion of the insulating layer and upwardly projecting vias in the upper portion of the layer.Type: GrantFiled: June 7, 1995Date of Patent: November 25, 1997Assignee: Advanced Micro Devices, Inc.Inventors: Steven Avanzino, Subhash Gupta, Rich Klein, Scott D. Luning, Ming-Ren Lin
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Patent number: 5686354Abstract: A dual damascene method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a thin protective via mask to form the via openings. A conductive line mask pattern is used to form conductive line openings in an insulating layer. Next, a thin protective layer of conformal material is deposited in the conducive line opening. The protective layer and the insulating layer each have etch resistance to others etchant. Using a via mask pattern, openings are etching the protective layer with the insulating layer serving as and etch stop. Next via openings are etched in the insulating material using the openings in the thin protective layer as the etch mask. If the protective layer is a conductive material, it is removed from the surface of the insulating layer either before or after the conductive line and via openings are filled with a conductive material.Type: GrantFiled: June 7, 1995Date of Patent: November 11, 1997Assignee: Advanced Micro Devices, Inc.Inventors: Steven Avanzino, Subhash Gupta, Rich Klein, Scott D. Luning, Ming-Ren Lin
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Patent number: 5614765Abstract: An interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using dual damascene with only one mask pattern for the formation of both the conductive lines and vias. The mask pattern of conductive lines contains laterally enlarged areas where the via openings are to formed in the insulating material. After the conductive line openings with laterally enlarged areas are created, the openings are filled with a conformal material whose etch selectivity is substantially less than the etch selectivity of the insulating material to the enchant for etching the insulating material and whose etch selectivity is substantially greater than the insulating material to its enchant. The conformal material is anisotropically etched to form sidewalls in the enlarged area and remove the material between the sidewalls but leave material remaining in the parts of the conductive lines openings.Type: GrantFiled: June 7, 1995Date of Patent: March 25, 1997Assignee: Advanced Micro Devices, Inc.Inventors: Steven Avanzino, Subhash Gupta, Rich Klein, Scott D. Luning, Ming-Ren Lin