Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes: a data detector circuit, a low latency detection circuit, and an error calculation circuit. The data detector circuit is operable to perform a data detection process on a first signal derived from a data input to yield a detected output, and to provide a loop error as a difference between the detected output and the first signal. The low latency detection circuit operable to process a second signal derived from the data input to yield a fast detector output, and to provide a generated error as a difference between the fast detector output and the second signal. The error calculation circuit is operable to calculate an error value based at least in part on the generated error and the loop error.

Abstract: Various embodiments of the present invention provide systems and methods for media defect detection. For example, a media defect detection systems is disclosed that includes a data input derived from a medium, a fast envelope calculation circuit that receives the data input and provides a fast decay envelope value based on the data input, a slow envelope calculation circuit that receives the data input and provides a slow decay envelope value based on the data input, and a media defect detection circuit. The media defect detection circuit receives the slow decay envelope value and the fast decay envelope value, calculates a ratio value of the fast decay envelope value to the slow decay envelope value, and asserts a defect output based at least in part on the comparison of the ratio value to a defect threshold value.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes first and second data detectors and an error cancellation circuit. The first data detector is operable to perform a data detection process on a first signal derived from a data input to yield a detected output. The second data detector circuit is operable to perform a data detection process on a second signal derived from the data input to yield a second detected output. The error cancellation circuit is operable to combine a first error signal derived from the detected output with a second error signal derived from the second detected output to yield a feedback signal. The feedback signal is operable to modify the data input during a subsequent period.

Abstract: Various embodiments of the present invention provide systems and methods for media defect detection. For example, a media defect detection systems is disclosed that includes a data input derived from a medium, a fast envelope calculation circuit that receives the data input and provides a fast decay envelope value based on the data input, a slow envelope calculation circuit that receives the data input and provides a slow decay envelope value based on the data input, and a media defect detection circuit. The media defect detection circuit receives the slow decay envelope value and the fast decay envelope value, calculates a ratio value of the fast decay envelope value to the slow decay envelope value, and asserts a defect output based at least in part on the comparison of the ratio value to a defect threshold value.

Abstract: Various embodiments of the present invention provide systems and methods for storage medium flaw detection. For example, some embodiments provide flaw detection systems that include an input circuit, a data processing circuit and a defect detection circuit. The input circuit is operable to receive an input signal and to provide a filtered output. The data processing circuit is operable to receive the filtered output and to compute a difference between the filtered output and an expected output, and the defect detection circuit receives the difference between the filtered output and the expected output and compares a derivative of the difference with a threshold value, and asserts a defect signal when a magnitude of the derivative of the difference exceeds a threshold value.

Abstract: Various embodiments of the present invention provide systems and methods for storage medium flaw detection. For example, some embodiments provide flaw detection systems that include an input circuit, a data processing circuit and a defect detection circuit. The input circuit is operable to receive an input signal and to provide a filtered output. The data processing circuit is operable to receive the filtered output and to compute a difference between the filtered output and an expected output, and the defect detection circuit receives the difference between the filtered output and the expected output and compares a derivative of the difference with a threshold value, and asserts a defect signal when a magnitude of the derivative of the difference exceeds a threshold value.

Abstract: Various embodiments of the present invention provide systems and methods for estimating signal and noise powers in a received signal set. For example, one embodiment of the present invention provides a method for determining signal power and noise power. The method uses a storage medium that includes a Na×Nw data pattern. The Na×Nw data pattern includes Na bits repeated Nw times. Both Na and Nw are each greater than one. The methods further include performing an initial read of the Na×Nw data pattern, which is stored to a first register.

Abstract: Various embodiments of the present invention provide systems and methods for media defect detection. For example, a media defect detection systems is disclosed that includes a data input derived from a medium, a fast envelope calculation circuit that receives the data input and provides a fast decay envelope value based on the data input, a slow envelope calculation circuit that receives the data input and provides a slow decay envelope value based on the data input, and a media defect detection circuit. The media defect detection circuit receives the slow decay envelope value and the fast decay envelope value, calculates a ratio value of the fast decay envelope value to the slow decay envelope value, and asserts a defect output based at least in part on the comparison of the ratio value to a defect threshold value.

Abstract: Connection lines are routed within an integrated circuit. A first set of the connection lines are pre-routed. The first set of connection lines carry signals which have a higher likelihood of being influenced by crosstalk. The first set of connection lines are routed to tracks where minimal capacitive coupling will result. For example, this may be in a track immediately adjacent to a power line or a ground line. Alternatively, or in addition, this may be in a track between two empty tracks. After the first set of connection lines have been routed, a second set of connection lines are routed. The second set of connection lines carry signals which have a lower likelihood of being influenced by crosstalk. The second connection lines are routed to tracks which are not utilized by the first set of connection lines.